132 lines
4.5 KiB
Plaintext
132 lines
4.5 KiB
Plaintext
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/*
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* arch/arm/boot/dts/panel-s-edp-uhdtv-15-6.dtsi
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <dt-bindings/display/tegra-dc.h>
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#include <dt-bindings/display/tegra-panel.h>
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/ {
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host1x {
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sor {
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panel_s_edp_uhdtv_15_6: panel-s-edp-uhdtv-15-6 {
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status = "disabled";
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compatible = "s-edp,uhdtv-15-6";
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nvidia,tx-pu-disable = <1>;
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disp-default-out {
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nvidia,out-type = <TEGRA_DC_OUT_DP>;
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nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
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nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
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nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
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nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
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TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
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TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
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TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
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nvidia,out-depth = <24>;
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nvidia,out-parent-clk = "pll_d_out0";
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nvidia,out-width = <346>;
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nvidia,out-height = <194>;
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nvidia,out-xres = <3840>;
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nvidia,out-yres = <2160>;
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};
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display-timings {
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3840x2160-32 {
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clock-frequency = <522090000>;
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hactive = <3840>;
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vactive = <2160>;
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hfront-porch = <48>;
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hback-porch = <80>;
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hsync-len = <32>;
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vfront-porch = <3>;
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vback-porch = <54>;
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vsync-len = <5>;
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nvidia,h-ref-to-sync = <1>;
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nvidia,v-ref-to-sync = <1>;
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};
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};
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dp-lt-settings {
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lt-setting@0 {
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nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
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nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
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nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
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nvidia,tx-pu = <0>;
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nvidia,load-adj = <0x3>;
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};
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lt-setting@1 {
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nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
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nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
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nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
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nvidia,tx-pu = <0>;
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nvidia,load-adj = <0x4>;
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};
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lt-setting@2 {
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nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
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nvidia,lane-preemphasis = <PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1>;
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nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
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nvidia,tx-pu = <0>;
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nvidia,load-adj = <0x6>;
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};
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};
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smartdimmer {
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status = "okay";
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nvidia,use-auto-pwm = <0>;
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nvidia,hw-update-delay = <0>;
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nvidia,bin-width = <0xffffffff>;
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nvidia,aggressiveness = <5>;
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nvidia,use-vid-luma = <0>;
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nvidia,phase-in-settings = <0>;
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nvidia,phase-in-adjustments = <0>;
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nvidia,k-limit-enable = <1>;
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nvidia,k-limit = <200>;
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nvidia,sd-window-enable = <0>;
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nvidia,soft-clipping-enable= <1>;
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nvidia,soft-clipping-threshold = <128>;
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nvidia,smooth-k-enable = <0>;
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nvidia,smooth-k-incr = <64>;
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nvidia,coeff = <5 9 2>;
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nvidia,fc = <0 0>;
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nvidia,blp = <1024 255>;
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nvidia,bltf = <57 65 73 82
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92 103 114 125
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138 150 164 178
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193 208 224 241>;
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nvidia,lut = <255 255 255
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199 199 199
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153 153 153
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116 116 116
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85 85 85
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59 59 59
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36 36 36
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17 17 17
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0 0 0>;
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nvidia,use-vpulse2 = <1>;
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nvidia,bl-device-name = "pwm-backlight";
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};
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};
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};
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};
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backlight {
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panel_s_edp_uhdtv_15_6_bl: panel-s-edp-uhdtv-15-6-bl {
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status = "disabled";
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compatible = "s-edp,uhdtv-15-6-bl";
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pwms = <&tegra_pwm 1 5000000>;
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max-brightness = <255>;
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default-brightness = <224>;
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};
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};
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};
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