179 lines
5.7 KiB
Plaintext
179 lines
5.7 KiB
Plaintext
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/*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "tegra210-pin-drive-sdmmc-common.dtsi"
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/ {
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aliases {
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sdhci0 = &sdmmc1;
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sdhci1 = &sdmmc2;
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sdhci2 = &sdmmc3;
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sdhci3 = &sdmmc4;
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};
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sdmmc4: sdhci@700b0600 {
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tap-delay = <4>;
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trim-delay = <8>;
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nvidia,is-ddr-tap-delay;
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nvidia,ddr-tap-delay = <0>;
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mmc-ocr-mask = <0>;
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max-clk-limit = <199680000>;
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bus-width = <8>;
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built-in;
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calib-3v3-offsets = <0x0505>;
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calib-1v8-offsets = <0x0505>;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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nvidia,en-io-trim-volt;
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nvidia,is-emmc;
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nvidia,enable-cq;
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ignore-pm-notify;
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keep-power-in-suspend;
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non-removable;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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nvidia,enable-strobe-mode;
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mmc-hs400-enhanced-strobe;
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nvidia,min-tap-delay = <106>;
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nvidia,max-tap-delay = <185>;
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pll_source = "pll_p", "pll_c4_out0";
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resets = <&tegra_car TEGRA210_CLK_SDMMC4>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
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<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
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clock-names = "sdmmc", "pll_p", "pll_c4_out0", "sdmmc_legacy_tm";
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};
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sdmmc3: sdhci@700b0400 {
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tap-delay = <1>;
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trim-delay = <3>;
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mmc-ocr-mask = <0>;
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max-clk-limit = <204000000>;
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ddr-clk-limit = <48000000>;
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bus-width = <4>;
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calib-3v3-offsets = <0x007D>;
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calib-1v8-offsets = <0x7B7B>;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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pll_source = "pll_p", "pll_c4_out2";
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resets = <&tegra_car TEGRA210_CLK_SDMMC3>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
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<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
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clock-names = "sdmmc", "pll_p", "pll_c4_out2", "sdmmc_legacy_tm";
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keep-power-in-suspend;
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ignore-pm-notify;
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non-removable;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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nvidia,en-io-trim-volt;
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nvidia,en-periodic-calib;
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cd-inverted;
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wp-inverted;
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pwrdet-support;
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nvidia,min-tap-delay = <106>;
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nvidia,max-tap-delay = <185>;
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pinctrl-names = "sdmmc_schmitt_enable", "sdmmc_schmitt_disable", "sdmmc_clk_schmitt_enable", "sdmmc_clk_schmitt_disable", "sdmmc_drv_code", "sdmmc_default_drv_code", "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
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pinctrl-0 = <&sdmmc3_schmitt_enable_state>;
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pinctrl-1 = <&sdmmc3_schmitt_disable_state>;
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pinctrl-2 = <&sdmmc3_clk_schmitt_enable_state>;
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pinctrl-3 = <&sdmmc3_clk_schmitt_disable_state>;
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pinctrl-4 = <&sdmmc3_drv_code_1_8V>;
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pinctrl-5 = <&sdmmc3_default_drv_code_3_3V>;
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pinctrl-6 = <&sdmmc3_e_33V_enable>;
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pinctrl-7 = <&sdmmc3_e_33V_disable>;
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};
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sdmmc2: sdhci@700b0200 {
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tap-delay = <4>;
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trim-delay = <8>;
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mmc-ocr-mask = <0>;
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max-clk-limit = <204000000>;
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ddr-clk-limit = <41000000>;
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bus-width = <4>;
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calib-3v3-offsets = <0x0505>;
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calib-1v8-offsets = <0x0505>;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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default-drive-type = <1>;
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nvidia,min-tap-delay = <106>;
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nvidia,max-tap-delay = <185>;
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pll_source = "pll_p";
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resets = <&tegra_car TEGRA210_CLK_SDMMC2>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
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clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
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non-removable;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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keep-power-in-suspend;
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ignore-pm-notify;
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nvidia,en-io-trim-volt;
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};
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sdmmc1: sdhci@700b0000 {
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tap-delay = <4>;
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trim-delay = <2>;
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max-clk-limit = <204000000>;
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ddr-clk-limit = <48000000>;
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bus-width = <4>;
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mmc-ocr-mask = <3>;
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calib-3v3-offsets = <0x007D>;
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calib-1v8-offsets = <0x7B7B>;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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cd-gpios = <&gpio TEGRA_GPIO(Z, 1) 0>;
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pll_source = "pll_p";
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cap-mmc-highspeed;
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cap-sd-highspeed;
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nvidia,en-io-trim-volt;
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nvidia,en-periodic-calib;
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keep-power-in-suspend;
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ignore-pm-notify;
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cd-inverted;
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wp-inverted;
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nvidia,min-tap-delay = <106>;
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nvidia,max-tap-delay = <185>;
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resets = <&tegra_car TEGRA210_CLK_SDMMC1>;
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reset-names = "sdhci";
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clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
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clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
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pwrdet-support;
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pinctrl-names = "sdmmc_schmitt_enable", "sdmmc_schmitt_disable", "sdmmc_clk_schmitt_enable", "sdmmc_clk_schmitt_disable", "sdmmc_drv_code", "sdmmc_default_drv_code", "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
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pinctrl-0 = <&sdmmc1_schmitt_enable_state>;
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pinctrl-1 = <&sdmmc1_schmitt_disable_state>;
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pinctrl-2 = <&sdmmc1_clk_schmitt_enable_state>;
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pinctrl-3 = <&sdmmc1_clk_schmitt_disable_state>;
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pinctrl-4 = <&sdmmc1_drv_code_1_8V>;
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pinctrl-5 = <&sdmmc1_default_drv_code_3_3V>;
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pinctrl-6 = <&sdmmc1_e_33V_enable>;
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pinctrl-7 = <&sdmmc1_e_33V_disable>;
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};
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};
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