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tegrakernel/hardware/nvidia/soc/t210/kernel-dts/tegra210-soc/tegra210-soc-base.dtsi

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initial commit tegra kernel 32.6.1
2022-02-16 09:13:02 -06:00
/*
* tegra210-soc-base.dtsi: SOC specific DTSI file with all node disabled.
*
* Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <dt-bindings/version.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/memory/tegra-swgroup.h>
#include "tegra210-thermal.dtsi"
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/soc/tegra-io-pads.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/ata/ahci-tegra.h>
#include <dt-bindings/soc/tegra210-powergate.h>
#include <dt-bindings/interrupt-controller/tegra-t21x-agic.h>
#include "tegra210-soc-power-domain.dtsi"
#include <dt-bindings/usb/tegra_xhci.h>
#include <dt-bindings/pinctrl/pinctrl-tegra21x-padctl-uphy.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include "tegra210-soc/tegra210-soc-actmon.dtsi"
/ {
compatible = "nvidia,tegra210";
interrupt-parent = <&lic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
sdhci0 = &sdhci0;
sdhci1 = &sdhci1;
sdhci2 = &sdhci2;
sdhci3 = &sdhci3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
status = "disabled";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57-64bit", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&C7>;
errata_hwcaps = <0x7>;
cpu-ipc = <1024>;
next-level-cache = <&L2>;
status = "disabled";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57-64bit", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&C7>;
errata_hwcaps = <0x7>;
cpu-ipc = <1024>;
next-level-cache = <&L2>;
status = "disabled";
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57-64bit", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&C7>;
errata_hwcaps = <0x7>;
cpu-ipc = <1024>;
next-level-cache = <&L2>;
status = "disabled";
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57-64bit", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&C7>;
errata_hwcaps = <0x7>;
cpu-ipc = <1024>;
next-level-cache = <&L2>;
status = "disabled";
};
idle-states {
entry-method = "psci";
C7: c7 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000007>;
wakeup-latency-us = <130>;
min-residency-us = <1000>;
idle-state-name = "c7-cpu-powergated";
status = "okay";
};
CC6: cc6 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x40000010>;
wakeup-latency-us = <230>;
min-residency-us = <10000>;
idle-state-name = "cc6-cluster-powergated";
status = "okay";
};
};
L2: l2-cache {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-1.0";
status = "disabled";
method = "smc";
};
tlk {
compatible = "android,tlk-driver";
status = "disabled";
log {
compatible = "android,ote-logger";
};
};
arm-pmu {
compatible = "arm,armv8-pmuv3";
status = "disabled";
interrupts = <0 144 0x4>,
<0 145 0x4>,
<0 146 0x4>,
<0 147 0x4>;
interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
&{/cpus/cpu@2} &{/cpus/cpu@3}>;
};
tegra_car: clock {
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
status = "enabled";
};
bwmgr {
compatible = "nvidia,bwmgr";
#if defined(LINUX_VERSION) && LINUX_VERSION >= 414
clocks = <&tegra_car TEGRA210_CLK_EMC>;
#else
clocks = <&tegra_car TEGRA210_CLK_BWMGR_EMC>;
nvidia,bwmgr-use-shared-master;
#endif
clock-names = "emc";
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
iram: iram-carveout {
compatible = "nvidia,iram-carveout";
reg = <0x0 0x40001000 0x0 0x3F000>;
no-map;
};
ramoops_reserved: ramoops_carveout {
compatible = "nvidia,ramoops";
reg = <0x0 0xb0000000 0x0 0x200000>;
no-map;
};
vpr: vpr-carveout {
compatible = "nvidia,vpr-carveout";
size = <0 0x19000000>;
alignment = <0 0x400000>;
alloc-ranges = <0x0 0x80000000 0x0 0x70000000>;
reusable;
};
fb0_reserved: fb0_carveout {
reg = <0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00>;
reg-names = "surface", "lut";
no-map;
};
fb1_reserved: fb1_carveout {
reg = <0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00>;
reg-names = "surface", "lut";
no-map;
};
};
tegra-carveouts {
compatible = "nvidia,carveouts";
iommus = <&smmu TEGRA_SWGROUP_HC>;
memory-region = <&vpr &iram>;
status = "okay";
};
smmu: iommu {
compatible = "nvidia,tegra210-smmu";
reg = <0x0 0x70019000 0x0 0x1000
0x0 0x6000c000 0x0 0x1000>;
status = "disabled";
#asids = <128>;
dma-window = <0x0 0x80000000 0x0 0x7ff00000>;
#iommu-cells = <1>;
swgid-mask = <0x00100fff 0xfffccdcf>;
#num-translation-enable = <5>;
#num-asid-security = <8>;
domains = <&ppcs_as TEGRA_SWGROUP_CELLS5(PPCS, PPCS1, PPCS2, SE, SE1)
&gpu_as TEGRA_SWGROUP_CELLS(GPUB)
&ape_as TEGRA_SWGROUP_CELLS(APE)
&dc_as TEGRA_SWGROUP_CELLS2(DC, DC12)
&dc_as TEGRA_SWGROUP_CELLS(DCB)
&common_as TEGRA_SWGROUP_CELLS(AFI)
&common_as TEGRA_SWGROUP_CELLS(SDMMC1A)
&common_as TEGRA_SWGROUP_CELLS(SDMMC2A)
&common_as TEGRA_SWGROUP_CELLS(SDMMC3A)
&common_as TEGRA_SWGROUP_CELLS(SDMMC4A)
&common_as TEGRA_SWGROUP_CELLS(AVPC)
&common_as TEGRA_SWGROUP_CELLS(SMMU_TEST)
&common_as 0xFFFFFFFF 0xFFFFFFFF>;
address-space-prop {
common_as: common {
iova-start = <0x0 0x80000000>;
iova-size = <0x0 0x7FF00000>;
num-pf-page = <0>;
gap-page = <1>;
};
ppcs_as: ppcs {
iova-start = <0x0 0x80000000>;
iova-size = <0x0 0x7FF00000>;
num-pf-page = <1>;
gap-page = <1>;
};
dc_as: dc {
iova-start = <0x0 0x00010000>;
iova-size = <0x0 0xFFFEFFFF>;
num-pf-page = <0>;
gap-page = <0>;
};
gpu_as: gpu {
iova-start = <0x0 0x00100000>;
iova-size = <0x3 0xFFEFFFFF>;
alignment = <0x20000>;
num-pf-page = <0>;
gap-page = <0>;
};
ape_as: ape {
iova-start = <0x0 0x70300000>;
iova-size = <0x0 0x8FC00000>;
num-pf-page = <0>;
gap-page = <1>;
};
};
};
smmu_test: smmu_test {
compatible = "nvidia,smmu_test";
iommus = <&smmu TEGRA_SWGROUP_SMMU_TEST>;
};
dma_test: dma_test {
compatible = "nvidia,dma_test";
};
bpmp {
compatible = "nvidia,tegra210-bpmp";
carveout-start = <0x80005000>;
carveout-size = <0x10000>;
resets = <&tegra_car 1>;
reset-names = "cop";
clocks = <&tegra_car TEGRA210_CLK_AVP_SCLK>;
clock-names = "sclk";
reg = <0x0 0x70016000 0x0 0x2000
0x0 0x60001000 0x0 0x1000>;
iommus = <&smmu TEGRA_SWGROUP_AVPC>;
status = "disabled";
};
mc {
compatible = "nvidia,tegra-mc";
reg-ranges = <10>; /* Per channel. */
reg = <0x0 0x70019000 0x0 0x00c>,
<0x0 0x70019050 0x0 0x19c>,
<0x0 0x70019200 0x0 0x024>,
<0x0 0x7001929c 0x0 0x1b8>,
<0x0 0x70019464 0x0 0x198>,
<0x0 0x70019604 0x0 0x3b0>,
<0x0 0x700199bc 0x0 0x020>,
<0x0 0x700199f8 0x0 0x08c>,
<0x0 0x70019ae4 0x0 0x0b0>,
<0x0 0x70019ba0 0x0 0x460>,
/* MC0 */
<0x0 0x7001c000 0x0 0x00c>,
<0x0 0x7001c050 0x0 0x198>,
<0x0 0x7001c200 0x0 0x024>,
<0x0 0x7001c29c 0x0 0x1b8>,
<0x0 0x7001c464 0x0 0x198>,
<0x0 0x7001c604 0x0 0x3b0>,
<0x0 0x7001c9bc 0x0 0x020>,
<0x0 0x7001c9f8 0x0 0x08c>,
<0x0 0x7001cae4 0x0 0x0b0>,
<0x0 0x7001cba0 0x0 0x460>,
/* MC1 */
<0x0 0x7001d000 0x0 0x00c>,
<0x0 0x7001d050 0x0 0x198>,
<0x0 0x7001d200 0x0 0x024>,
<0x0 0x7001d29c 0x0 0x1b8>,
<0x0 0x7001d464 0x0 0x198>,
<0x0 0x7001d604 0x0 0x3b0>,
<0x0 0x7001d9bc 0x0 0x020>,
<0x0 0x7001d9f8 0x0 0x08c>,
<0x0 0x7001dae4 0x0 0x0b0>,
<0x0 0x7001dba0 0x0 0x460>;
interrupts = <0 77 0x4>;
int_mask = <0x23D40>;
channels = <2>;
status = "disabled";
};
intc: interrupt-controller {
compatible = "arm,cortex-a15-gic";
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x50041000 0x0 0x1000
0x0 0x50042000 0x0 0x0100>;
status = "disabled";
};
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra210-ictlr";
interrupt-parent = <&intc>;
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x60004000 0x0 0x40>,
<0x0 0x60004100 0x0 0x40>,
<0x0 0x60004200 0x0 0x40>,
<0x0 0x60004300 0x0 0x40>,
<0x0 0x60004400 0x0 0x40>,
<0x0 0x60004500 0x0 0x40>;
interrupts = <0 4 4
0 5 4
0 7 4
0 18 4>;
outgoing-doorbell = <6>;
status = "disabled";
};
flow-controller@60007000 {
compatible = "nvidia,tegra210-flowctrl";
reg = <0x0 0x60007000 0x0 0x1000>;
};
ahb: ahb@6000c000 {
compatible = "nvidia,tegra210-ahb", "nvidia,tegra30-ahb";
reg = <0x0 0x6000c000 0x0 0x14f>;
status = "disabled";
};
#if TEGRA_AUDIO_BUS_DT_VERSION >= DT_VERSION_2
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
tegra_agic: agic@702f9000 {
compatible = "nvidia,tegra210-agic";
#interrupt-cells = <4>;
interrupt-controller;
reg = <0x0 0x702f9000 0x0 0x2000>,
<0x0 0x702fa000 0x0 0x2000>;
interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car TEGRA210_CLK_APE>;
clock-names = "clk";
};
adsp {
compatible = "nvidia,tegra210-adsp";
wakeup-disable;
interrupt-parent = <&tegra_agic>;
reg = <0x0 0x702ef000 0x0 0x1000>, /* AMC */
<0x0 0x702ec000 0x0 0x2000>, /* AMISC */
<0x0 0x702ee000 0x0 0x1000>, /* ABRIDGE */
<0x0 0x702dc800 0x0 0x0>, /* FPGA RESET REG */
<0x0 0x0 0x0 0x1>, /* AHSP */
<0x0 0x01000000 0x0 0x6f2c0000>, /* DRAM MAP1 */
<0x0 0x70300000 0x0 0x8fd00000>; /* DRAM MAP2 */
iommus = <&smmu TEGRA_SWGROUP_APE>;
dma-mask = <0x0 0xfff00000>;
iommu-resv-regions = <0x0 0x0 0x0 0x70300000 0x0 0xfff00000 0xffffffff 0xffffffff>;
iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
nvidia,adsp_mem = <0x80300000 0x01000000>, /* ADSP OS */
<0x80B00000 0x00800000>, /* ADSP APP */
<0x00400000 0x00010000>, /* ARAM ALIAS 0 */
<0x80300000 0x00200000>; /* ACSR */
nvidia,adsp-evp-base = <0x702ef700 0x00000040>;
interrupts = <GIC_SPI INT_AMISC_MBOX_EMPTY1 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* MBOX SEND */
<GIC_SPI INT_AMISC_MBOX_FULL0 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* MBOX RECV */
<GIC_SPI INT_ADSP_WDT IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* Watchdog */
<GIC_SPI INT_WFI IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* WFI */
<GIC_SPI INT_AMC_ERR IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* AMC ERR IRQ */
<GIC_SPI INT_ADSP_ACTMON IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* ADSP ACTMON IRQ */
<GIC_SPI INT_AMISC_MBOX_EMPTY0 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>, /* ADSP MBOX SEND */
<GIC_SPI INT_AMISC_MBOX_FULL1 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>, /* ADSP MBOX RECV */
<GIC_SPI INT_AMISC_MBOX_FULL2 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>; /* ADSP FIQ HANDLER */
clocks = <&tegra_car TEGRA210_CLK_ADSP_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>,
<&tegra_car TEGRA210_CLK_ADSP_NEON>,
<&tegra_car TEGRA210_CLK_ADSP>,
<&tegra_car TEGRA210_CLK_ADSP_CPU_ABUS>;
clock-names = "adsp.ape", "adsp.apb2ape", "adspneon",
"adsp", "adsp_cpu_abus";
resets = <&tegra_car TEGRA210_RST_ADSP>;
reset-names = "adspall";
nvidia,adsp_unit_fpga_reset = <0x0 0x00000040>;
status = "disabled";
};
};
#else
tegra_agic: agic-controller {
compatible = "nvidia,tegra210-agic";
interrupt-controller;
#interrupt-cells = <4>;
no-gic-extension;
not-per-cpu;
reg = <0x0 0x702f9000 0x0 0x2000>,
<0x0 0x702fa000 0x0 0x2000>,
<0x0 0x60006000 0x0 0x1000>;
enable-agic-clks;
interrupts = <0 102 0xf04>;
status = "disabled";
};
adsp {
compatible = "nvidia,tegra210-adsp";
wakeup-disable;
interrupt-parent = <&tegra_agic>;
reg = <0x0 0x702ef000 0x0 0x1000>, /* AMC */
<0x0 0x702ec000 0x0 0x2000>, /* AMISC */
<0x0 0x702ee000 0x0 0x1000>, /* ABRIDGE */
<0x0 0x702dc800 0x0 0x0>, /* FPGA RESET REG */
<0x0 0x0 0x0 0x1>, /* AHSP */
<0x0 0x01000000 0x0 0x6f2c0000>, /* DRAM MAP1 */
<0x0 0x70300000 0x0 0x8fd00000>; /* DRAM MAP2 */
iommus = <&smmu TEGRA_SWGROUP_APE>;
dma-mask = <0x0 0xfff00000>;
iommu-resv-regions = <0x0 0x0 0x0 0x70300000 0x0 0xfff00000 0xffffffff 0xffffffff>;
power-domains = <&adsp_pd>;
nvidia,adsp_mem = <0x80300000 0x01000000>, /* ADSP OS */
<0x80B00000 0x00800000>, /* ADSP APP */
<0x00400000 0x00010000>, /* ARAM ALIAS 0 */
<0x80300000 0x00200000>; /* ACSR */
nvidia,adsp-evp-base = <0x702ef700 0x00000040>;
interrupts = <GIC_SPI INT_AMISC_MBOX_EMPTY1 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* MBOX SEND */
<GIC_SPI INT_AMISC_MBOX_FULL0 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* MBOX RECV */
<GIC_SPI INT_ADSP_WDT IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* Watchdog */
<GIC_SPI INT_WFI IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* WFI */
<GIC_SPI INT_AMC_ERR IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* AMC ERR IRQ */
<GIC_SPI INT_ADSP_ACTMON IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_HOST>, /* ADSP ACTMON IRQ */
<GIC_SPI INT_AMISC_MBOX_EMPTY0 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>, /* ADSP MBOX SEND */
<GIC_SPI INT_AMISC_MBOX_FULL1 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>, /* ADSP MBOX RECV */
<GIC_SPI INT_AMISC_MBOX_FULL2 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>; /* ADSP FIQ HANDLER */
clocks = <&tegra_car TEGRA210_CLK_ADSP_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>,
<&tegra_car TEGRA210_CLK_ADSP_NEON>,
<&tegra_car TEGRA210_CLK_ADSP>,
<&tegra_car TEGRA210_CLK_APE_EMC>,
<&tegra_car TEGRA210_CLK_ADSP_CPU_ABUS>;
clock-names = "adsp.ape", "adsp.apb2ape", "adspneon",
"adsp", "adsp.emc", "adsp_cpu_abus";
resets = <&tegra_car TEGRA210_RST_ADSP>;
reset-names = "adspall";
nvidia,adsp_unit_fpga_reset = <0x0 0x00000040>;
status = "disabled";
};
#endif
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
status = "disabled";
};
timer@60005000 {
compatible = "nvidia,tegra210-timer", "nvidia,tegra30-timer",
"nvidia,tegra30-timer-wdt";
reg = <0x0 0x60005000 0x0 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TIMER>;
status = "disabled";
};
rtc {
compatible = "nvidia,tegra-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <0 2 0x04>;
status = "disabled";
};
apbdma: dma@60020000 {
compatible = "nvidia,tegra148-apbdma";
reg = <0x0 0x60020000 0x0 0x1400>;
clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
clock-names = "dma";
resets = <&tegra_car TEGRA210_CLK_APBDMA>;
reset-names = "dma";
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04
0 128 0x04
0 129 0x04
0 130 0x04
0 131 0x04
0 132 0x04
0 133 0x04
0 134 0x04
0 135 0x04
0 136 0x04
0 137 0x04
0 138 0x04
0 139 0x04
0 140 0x04
0 141 0x04
0 142 0x04
0 143 0x04>;
#dma-cells = <1>;
status = "disabled";
};
pinmux: pinmux@700008d4 {
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x2a5 /* Pad control registers */
0x0 0x70003000 0x0 0x294>; /* Mux registers */
#gpio-range-cells = <3>;
status = "disabled";
};
gpio: gpio@6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04
0 125 0x04>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
gpio-ranges = <&pinmux 0 0 246>;
status = "disabled";
};
xotg {
compatible = "nvidia,tegra210-xotg";
interrupts = <0 49 0x04
0 20 0x04>;
status = "disabled";
};
xusb_mbox: mailbox@70098000 {
compatible = "nvidia,tegra210-xusb-mbox";
reg = <0x0 0x70098000 0x0 0x1000>;
interrupts = <0x0 0x28 0x4>;
#mbox-cells = <0>;
status = "disabled";
};
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
xusb_padctl: xusb_padctl@7009f000 {
compatible = "nvidia,tegra210-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
reg-names = "padctl";
resets = <&tegra_car 142>;
reset-names = "padctl";
status = "disabled";
pads {
usb2 {
clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
usb2-0 {
status = "disabled";
#phy-cells = <0>;
};
usb2-1 {
status = "disabled";
#phy-cells = <0>;
};
usb2-2 {
status = "disabled";
#phy-cells = <0>;
};
usb2-3 {
status = "disabled";
#phy-cells = <0>;
};
};
};
pcie {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "pll";
resets = <&tegra_car 205>;
reset-names = "phy";
status = "disabled";
lanes {
pcie-0 {
status = "disabled";
#phy-cells = <0>;
};
pcie-1 {
status = "disabled";
#phy-cells = <0>;
};
pcie-2 {
status = "disabled";
#phy-cells = <0>;
};
pcie-3 {
status = "disabled";
#phy-cells = <0>;
};
pcie-4 {
status = "disabled";
#phy-cells = <0>;
};
pcie-5 {
status = "disabled";
#phy-cells = <0>;
};
pcie-6 {
status = "disabled";
#phy-cells = <0>;
};
};
};
sata {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "pll";
resets = <&tegra_car 204>;
reset-names = "phy";
status = "disabled";
lanes {
sata-0 {
status = "disabled";
#phy-cells = <0>;
};
};
};
hsic {
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
hsic-0 {
status = "disabled";
#phy-cells = <0>;
};
};
};
};
ports {
usb2-0 {
status = "disabled";
};
usb2-1 {
status = "disabled";
};
usb2-2 {
status = "disabled";
};
usb2-3 {
status = "disabled";
};
usb3-0 {
status = "disabled";
};
usb3-1 {
status = "disabled";
};
usb3-2 {
status = "disabled";
};
usb3-3 {
status = "disabled";
};
hsic-0 {
status = "disabled";
};
};
};
#endif
tegra_usb_cd: usb_cd {
compatible = "nvidia,tegra210-usb-cd";
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
nvidia,xusb-padctl = <&xusb_padctl>;
#endif
status = "disabled";
};
tegra_padctl_uphy: pinctrl@7009f000 {
compatible = "nvidia,tegra21x-padctl-uphy";
reg = <0x0 0x7009f000 0x0 0x1000>;
reg-names = "padctl";
resets = <&tegra_car 142>, <&tegra_car 204>, <&tegra_car 205>;
reset-names = "padctl", "sata_uphy", "pex_uphy";
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>,
<&tegra_car TEGRA210_CLK_USB2_TRK>,
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "hsic_trk", "usb2_trk", "pll_e";
interrupts = <0 49 0x04>;
mboxes = <&xusb_mbox>;
mbox-names = "xusb";
#phy-cells = <1>;
status = "disabled";
};
xusb@70090000 {
compatible = "nvidia,tegra210-xhci";
reg = <0x0 0x70090000 0x0 0x8000>,
<0x0 0x70098000 0x0 0x1000>,
<0x0 0x70099000 0x0 0x1000>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
interrupts = <0 39 0x04>, <0 40 0x04>, <0 49 0x04>;
nvidia,xusb-padctl = <&xusb_padctl>;
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
<&tegra_car TEGRA210_CLK_CLK_M>,
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", "xusb_ss_src", "xusb_hs_src",
"xusb_fs_src", "pll_u_480m", "clk_m", "pll_e";
#else
interrupts = <0 39 0x04>, <0 49 0x04>;
mboxes = <&xusb_mbox>;
mbox-names = "xusb";
#endif
iommus = <&smmu TEGRA_SWGROUP_XUSB_HOST>;
status = "disabled";
};
tegra_ext_cdp: max16984-cdp {
compatible = "maxim,max16984-tegra210-cdp-phy";
#phy-cells = <1>;
status = "disabled";
};
uarta: serial@70006000 {
compatible = "nvidia,tegra114-hsuart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_UARTA>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "serial", "parent";
resets = <&tegra_car TEGRA210_CLK_UARTA>;
reset-names = "serial";
nvidia,adjust-baud-rates = <115200 115200 100>;
status = "disabled";
};
uartb: serial@70006040 {
compatible = "nvidia,tegra114-hsuart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
dmas = <&apbdma 9>, <&apbdma 9>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_UARTB>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "serial", "parent";
resets = <&tegra_car TEGRA210_RST_UARTB>;
reset-names = "serial";
nvidia,adjust-baud-rates = <115200 115200 100>;
status = "disabled";
};
uartc: serial@70006200 {
compatible = "nvidia,tegra114-hsuart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
dmas = <&apbdma 10>, <&apbdma 10>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_UARTC>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "serial", "parent";
resets = <&tegra_car TEGRA210_CLK_UARTC>;
reset-names = "serial";
nvidia,adjust-baud-rates = <115200 115200 100>;
status = "disabled";
};
uartd: serial@70006300 {
compatible = "nvidia,tegra114-hsuart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
dmas = <&apbdma 19>, <&apbdma 19>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_UARTD>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "serial", "parent";
resets = <&tegra_car TEGRA210_CLK_UARTD>;
reset-names = "serial";
nvidia,adjust-baud-rates = <115200 115200 100>;
status = "disabled";
};
sound {
iommus = <&smmu TEGRA_SWGROUP_APE>;
dma-mask = <0x0 0xfff00000>;
iommu-resv-regions = <0x0 0x0 0x0 0x70300000 0x0 0xFFF00000 0xffffffff 0xffffffff>;
iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
status = "disabled";
};
sound_ref {
iommus = <&smmu TEGRA_SWGROUP_APE>;
dma-mask = <0x0 0xfff00000>;
iommu-resv-regions = <0x0 0x0 0x0 0x70300000 0x0 0xFFF00000 0xffffffff 0xffffffff>;
iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
status = "disabled";
};
tegra_pwm: pwm@7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_PWM>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "pwm", "parent";
resets = <&tegra_car TEGRA210_CLK_PWM>;
reset-names = "pwm";
};
spi0: spi@7000d400 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
interrupts = <0 59 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
nvidia,clk-parents = "pll_p", "clk_m";
clocks = <&tegra_car TEGRA210_CLK_SBC1>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_CLK_M>;
clock-names = "spi", "pll_p", "clk_m";
resets = <&tegra_car TEGRA210_CLK_SBC1>;
reset-names = "spi";
status = "disabled";
};
spi1: spi@7000d600 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <0 82 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
nvidia,clk-parents = "pll_p", "clk_m";
clocks = <&tegra_car TEGRA210_CLK_SBC2>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_CLK_M>;
clock-names = "spi", "pll_p", "clk_m";
resets = <&tegra_car TEGRA210_CLK_SBC2>;
reset-names = "spi";
status = "disabled";
};
spi2: spi@7000d800 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
interrupts = <0 83 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
nvidia,clk-parents = "pll_p", "clk_m";
clocks = <&tegra_car TEGRA210_CLK_SBC3>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_CLK_M>;
clock-names = "spi", "pll_p", "clk_m";
resets = <&tegra_car TEGRA210_CLK_SBC3>;
reset-names = "spi";
status = "disabled";
};
spi3: spi@7000da00 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
interrupts = <0 93 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
nvidia,clk-parents = "pll_p", "clk_m";
clocks = <&tegra_car TEGRA210_CLK_SBC4>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_CLK_M>;
clock-names = "spi", "pll_p", "clk_m";
resets = <&tegra_car TEGRA210_CLK_SBC4>;
reset-names = "spi";
status = "disabled";
};
qspi6: spi@70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x0 0x70410000 0x0 0x1000>;
interrupts = <0 10 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&apbdma 5>, <&apbdma 5>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_QSPI>,
<&tegra_car TEGRA210_CLK_QSPI_OUT>;
clock-names = "qspi","qspi_out";
resets = <&tegra_car TEGRA210_CLK_QSPI>;
reset-names = "qspi";
status = "disabled";
};
host1x: host1x {
compatible = "nvidia,tegra210-host1x", "simple-bus";
#if defined(LINUX_VERSION) && LINUX_VERSION < 414
power-domains = <&host1x_pd>;
#endif
wakeup-capable;
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <0 65 0x04 /* mpcore syncpt */
0 67 0x04>; /* mpcore general */
iommus = <&smmu TEGRA_SWGROUP_HC>;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
ranges;
clocks = <&tegra_car TEGRA210_CLK_NV_HOST1X>,
<&tegra_car TEGRA210_CLK_ACTMON>;
clock-names = "host1x", "actmon";
resets = <&tegra_car TEGRA210_CLK_HOST1X>;
nvidia,ch-base = <0>;
nvidia,nb-channels = <12>;
nvidia,nb-hw-pts = <192>;
nvidia,pts-base = <0>;
nvidia,nb-pts = <192>;
vi {
compatible = "nvidia,tegra210-vi", "simple-bus";
power-domains = <&ve_pd>;
reg = <0x0 0x54080000 0x0 0x40000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu TEGRA_SWGROUP_VI>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_VI_V4L2_CBUS>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_VI_I2C>,
<&tegra_car TEGRA210_CLK_I2CSLOW>,
<&tegra_car TEGRA210_CLK_PLL_D>,
<&tegra_car TEGRA210_CLK_PLL_D_DSI_OUT>;
clock-names = "vi", "csi", "cilab", "cilcd",
"cile", "vii2c", "i2cslow",
"pll_d", "pll_d_dsi_out";
resets = <&tegra_car 20>;
reset-names = "vi";
#address-cells = <1>;
#size-cells = <0>;
};
vi-bypass {
compatible = "nvidia,tegra210-vi-bypass";
status = "okay";
};
isp@54600000 {
compatible = "nvidia,tegra210-isp";
power-domains = <&ve_pd>;
reg = <0x0 0x54600000 0x0 0x00040000>;
interrupts = <0 71 0x04>;
iommus = <&smmu TEGRA_SWGROUP_ISP>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_ISPA_ISP_CBUS>;
clock-names = "ispa";
resets = <&tegra_car TEGRA210_CLK_ISPA>;
};
isp@54680000 {
compatible = "nvidia,tegra210-isp";
power-domains = <&pd_ve2>;
reg = <0x0 0x54680000 0x0 0x00040000>;
interrupts = <0 70 0x04>;
iommus = <&smmu TEGRA_SWGROUP_ISP2B>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_ISPB_ISP_CBUS>;
clock-names = "ispb";
resets = <&tegra_car TEGRA210_CLK_ISPB>;
};
head0: dc@54200000 {
compatible = "nvidia,tegra210-dc";
aux-device-name = "tegradc.0";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <0 73 0x04>;
win-mask = <0xf>;
nvidia,fb-win = <0>;
iommus = <&smmu TEGRA_SWGROUP_DC>,
<&smmu TEGRA_SWGROUP_DC12>;
clocks = <&tegra_car TEGRA210_CLK_DISP1>,
<&tegra_car TEGRA210_CLK_TIMER>,
<&tegra_car TEGRA210_CLK_DISP1_EMC>,
<&tegra_car TEGRA210_CLK_DISP1_LA_EMC>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT3>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_D>;
clock-names = "disp1", "timer", "disp1_emc", "disp1_la_emc", "pll_p_out3", "pll_d_out0", "pll_d";
resets = <&tegra_car TEGRA210_CLK_DISP1>;
reset-names = "dc_rst";
status = "disabled";
nvidia,dc-ctrlnum = <0>;
fb_reserved = <&fb0_reserved>;
iommu-direct-regions = <&fb0_reserved>;
pinctrl-names = "dsi-dpd-disable", "dsi-dpd-enable",
"dsib-dpd-disable", "dsib-dpd-enable",
"hdmi-dpd-disable", "hdmi-dpd-enable";
pinctrl-0 = <&dsi_dpd_disable>;
pinctrl-1 = <&dsi_dpd_enable>;
pinctrl-2 = <&dsib_dpd_disable>;
pinctrl-3 = <&dsib_dpd_enable>;
pinctrl-4 = <&hdmi_dpd_disable>;
pinctrl-5 = <&hdmi_dpd_enable>;
rgb {
status = "disabled";
};
};
head1: dc@54240000 {
compatible = "nvidia,tegra210-dc";
aux-device-name = "tegradc.1";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <0 74 0x04>;
win-mask = <0x7>;
nvidia,fb-win = <0>;
iommus = <&smmu TEGRA_SWGROUP_DCB>;
status = "disabled";
nvidia,dc-ctrlnum = <1>;
clocks = <&tegra_car TEGRA210_CLK_DISP2>,
<&tegra_car TEGRA210_CLK_TIMER>,
<&tegra_car TEGRA210_CLK_DISP2_EMC>,
<&tegra_car TEGRA210_CLK_DISP2_LA_EMC>,
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_D2>;
clock-names = "disp2", "timer", "disp2_emc", "disp2_la_emc", "pll_d2_out0", "pll_d2";
resets = <&tegra_car TEGRA210_CLK_DISP2>;
reset-names = "dc_rst";
fb_reserved = <&fb1_reserved>;
iommu-direct-regions = <&fb1_reserved>;
pinctrl-names = "dsi-dpd-disable", "dsi-dpd-enable",
"dsib-dpd-disable", "dsib-dpd-enable",
"hdmi-dpd-disable", "hdmi-dpd-enable";
pinctrl-0 = <&dsi_dpd_disable>;
pinctrl-1 = <&dsi_dpd_enable>;
pinctrl-2 = <&dsib_dpd_disable>;
pinctrl-3 = <&dsib_dpd_enable>;
pinctrl-4 = <&hdmi_dpd_disable>;
pinctrl-5 = <&hdmi_dpd_enable>;
rgb {
status = "disabled";
};
};
dsi: dsi {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x00040000
0x0 0x54400000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIALP>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DSIBLP>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT3>,
<&tegra_car TEGRA210_CLK_CLK72MHZ>;
clock-names = "dsi", "dsia_lp", "dsib", "dsib_lp", "pll_p_out3", "clk72mhz";
resets = <&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>;
reset-names = "dsia", "dsib";
status = "disabled";
};
vic {
compatible = "nvidia,tegra210-vic";
power-domains = <&pd_vic>;
reg = <0x0 0x54340000 0x0 0x00040000>;
iommus = <&smmu TEGRA_SWGROUP_VIC>;
iommu-group-id = <TEGRA_IOMMU_GROUP_HOST1X>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_VIC03_CBUS>,
<&tegra_car TEGRA210_CLK_VIC_EMC>,
<&tegra_car TEGRA210_CLK_VIC_FLOOR_CBUS>,
<&tegra_car TEGRA210_CLK_VIC_SHARED_EMC>;
clock-names = "vic03", "emc", "vic_floor",
"emc_shared";
resets = <&tegra_car TEGRA210_CLK_VIC03>;
};
nvenc {
compatible = "nvidia,tegra210-nvenc";
power-domains = <&pd_nvenc>;
reg = <0x0 0x544c0000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_NVENC_CBUS>;
clock-names = "msenc";
resets = <&tegra_car TEGRA210_CLK_NVENC>;
iommus = <&smmu TEGRA_SWGROUP_MPE>;
iommu-group-id = <TEGRA_IOMMU_GROUP_HOST1X>;
status = "disabled";
};
tsec {
compatible = "nvidia,tegra210-tsec";
#if defined(LINUX_VERSION) && LINUX_VERSION < 414
power-domains = <&tsec_pd>;
#endif
reg = <0x0 0x54500000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_TSEC>;
clock-names = "tsec";
resets = <&tegra_car TEGRA210_CLK_TSEC>;
iommus = <&smmu TEGRA_SWGROUP_TSEC>;
iommu-group-id = <TEGRA_IOMMU_GROUP_HOST1X>;
status = "disabled";
};
tsecb {
compatible = "nvidia,tegra210-tsec";
#if defined(LINUX_VERSION) && LINUX_VERSION < 414
power-domains = <&tsec_pd>;
#endif
reg = <0x0 0x54100000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_TSECB_CBUS>;
clock-names = "tsecb";
resets = <&tegra_car TEGRA210_CLK_TSECB>;
iommus = <&smmu TEGRA_SWGROUP_TSECB>;
iommu-group-id = <TEGRA_IOMMU_GROUP_HOST1X>;
status = "disabled";
};
nvdec {
compatible = "nvidia,tegra210-nvdec";
power-domains = <&pd_nvdec>;
reg = <0x0 0x54480000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_NVDEC_CBUS>;
clock-names = "nvdec";
resets = <&tegra_car TEGRA210_CLK_NVDEC>;
iommus = <&smmu TEGRA_SWGROUP_NVDEC>;
iommu-group-id = <TEGRA_IOMMU_GROUP_HOST1X>;
status = "disabled";
};
nvjpg {
compatible = "nvidia,tegra210-nvjpg";
power-domains = <&pd_nvjpg>;
reg = <0x0 0x54380000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_NVJPG_CBUS>;
clock-names = "nvjpg";
resets = <&tegra_car TEGRA210_CLK_NVJPG>;
iommus = <&smmu TEGRA_SWGROUP_NVJPG>;
iommu-group-id = <TEGRA_IOMMU_GROUP_HOST1X>;
status = "disabled";
};
sor0: sor {
compatible = "nvidia,tegra210-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
reg-names = "sor";
status = "disabled";
nvidia,sor-ctrlnum = <0>;
nvidia,dpaux = <&dpaux0>;
nvidia,xbar-ctrl = <2 1 0 3 4>;
clocks = <&tegra_car TEGRA210_CLK_SOR_SAFE>,
<&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_PLL_DP>;
clock-names = "sor_safe", "sor0", "pll_dp";
resets = <&tegra_car TEGRA210_CLK_SOR0>;
reset-names = "sor0";
nvidia,sor-audio-not-supported;
sor0_hdmi_display: hdmi-display {
compatible = "hdmi,display";
status = "disabled";
};
sor0_dp_display: dp-display {
compatible = "dp, display";
status = "disabled";
};
};
sor1: sor1 {
compatible = "nvidia,tegra210-sor1";
reg = <0x0 0x54580000 0x0 0x00040000>;
reg-names = "sor";
interrupts = <0 76 0x4>; /* INT_SOR_1 */
status = "disabled";
nvidia,sor-ctrlnum = <1>;
nvidia,dpaux = <&dpaux1>;
nvidia,xbar-ctrl = <2 1 0 3 4>;
clocks = <&tegra_car TEGRA210_CLK_SOR1_MUX>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>,
<&tegra_car TEGRA210_CLK_SOR1_BRICK>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_MAUD>,
<&tegra_car TEGRA210_CLK_HDA>,
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>,
<&tegra_car TEGRA210_CLK_HDA2HDMI>;
clock-names = "sor1_ref", "sor_safe", "sor1_pad_clkout",
"sor1", "pll_dp", "pll_p", "maud", "hda",
"hda2codec_2x", "hda2hdmi";
resets = <&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_HDA>,
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>,
<&tegra_car TEGRA210_CLK_HDA2HDMI>;
reset-names = "sor1", "hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst";
sor1_hdmi_display: hdmi-display {
compatible = "hdmi,display";
disp-default-out {
nvidia,out-xres = <4096>;
nvidia,out-yres = <2160>;
};
};
sor1_dp_display: dp-display {
compatible = "dp, display";
status = "disabled";
};
};
dpaux0: dpaux {
compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <0 159 0x4>; /* INT_DPAUX */
nvidia,dpaux-ctrlnum = <0>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_DPAUX>;
clock-names = "dpaux";
resets = <&tegra_car TEGRA210_CLK_DPAUX>;
reset-names = "dpaux";
};
dpaux1: dpaux1 {
compatible = "nvidia,tegra210-dpaux1";
reg = <0x0 0x54040000 0x0 0x00040000>;
interrupts = <0 11 0x4>; /* INT_DPAUX_1 */
nvidia,dpaux-ctrlnum = <1>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_DPAUX1>;
clock-names = "dpaux1";
resets = <&tegra_car TEGRA210_CLK_DPAUX1>;
reset-names = "dpaux1";
};
i2c7: i2c@546c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-vii2c";
reg = <0x0 0x546C0000 0x0 0x00034000>;
iommus = <&smmu TEGRA_SWGROUP_VII2C>;
interrupts = <0 17 0x04>;
scl-gpio = <&gpio TEGRA_GPIO(S, 2) 0>;
sda-gpio = <&gpio TEGRA_GPIO(S, 3) 0>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
<&tegra_car TEGRA210_CLK_I2CSLOW>,
<&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "vii2c", "i2cslow", "host1x";
resets = <&tegra_car 208>;
reset-names = "vii2c";
clock-frequency = <400000>;
};
};
gpu {
compatible = "nvidia,tegra210-gm20b", "nvidia,gm20b";
nvidia,host1x = <&host1x>;
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>,
<0x0 0x538f0000 0x0 0x00001000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
iommus = <&smmu TEGRA_SWGROUP_GPUB>;
access-vpr-phys;
status = "disabled";
resets = <&tegra_car TEGRA210_CLK_GPU>;
reset-names = "gpu";
};
mipical {
compatible = "nvidia,tegra210-mipical";
reg = <0x0 0x700e3000 0x0 0x00000100>;
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>,
<&tegra_car TEGRA210_CLK_CLK72MHZ>;
clock-names = "mipi_cal", "uart_mipi_cal";
status = "disabled";
assigned-clocks = <&tegra_car TEGRA210_CLK_CLK72MHZ>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <68000000>;
};
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
#padcontroller-cells = <1>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_PCLK>;
clock-names = "pclk";
nvidia,secure-pmc;
pex_io_dpd_disable_state: pex_en {
pex-io-dpd-signals-dis {
pins = "pex-bias", "pex-clk1", "pex-clk2";
low-power-disable;
};
};
pex_io_dpd_enable_state: pex_dis {
pex-io-dpd-signals-en {
pins = "pex-bias", "pex-clk1", "pex-clk2";
low-power-enable;
};
};
hdmi_dpd_enable: hdmi-dpd-enable {
hdmi-pad-lowpower-enable {
pins = "hdmi";
low-power-enable;
};
};
hdmi_dpd_disable: hdmi-dpd-disable {
hdmi-pad-lowpower-disable {
pins = "hdmi";
low-power-disable;
};
};
dsi_dpd_enable: dsi-dpd-enable {
dsi-pad-lowpower-enable {
pins = "dsi";
low-power-enable;
};
};
dsi_dpd_disable: dsi-dpd-disable {
dsi-pad-lowpower-disable {
pins = "dsi";
low-power-disable;
};
};
dsib_dpd_enable: dsib-dpd-enable {
dsib-pad-lowpower-enable {
pins = "dsib";
low-power-enable;
};
};
dsib_dpd_disable: dsib-dpd-disable {
dsib-pad-lowpower-disable {
pins = "dsib";
low-power-disable;
};
};
};
se: se@70012000 {
compatible = "nvidia,tegra210-se";
reg = <0x0 0x70012000 0x0 0x2000>; /* SE base */
iommus = <&smmu TEGRA_SWGROUP_SE>,
<&smmu TEGRA_SWGROUP_SE1>;
iommu-group-id = <TEGRA_IOMMU_GROUP_SE>;
interrupts = <0 58 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SE_CBUS>,
<&tegra_car TEGRA210_CLK_ENTROPY>;
clock-names = "se", "entropy";
status = "disabled";
};
#if TEGRA_AUDIO_BUS_DT_VERSION >= DT_VERSION_2
aconnect@702c0000 {
#address-cells = <2>;
#size-cells = <2>;
#endif
adma: adma@702e2000 {
compatible = "nvidia,tegra210-adma";
interrupt-parent = <&tegra_agic>;
reg = <0x0 0x702e2000 0x0 0x2000>, /* CH and GLOBAL Reg */
<0x0 0x702ec000 0x0 0x72>; /* AMISC Reg */
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
interrupts = <GIC_SPI INT_ADMA_EOT0 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT1 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT2 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT3 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT4 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT5 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT6 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT7 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT8 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT9 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT10 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT11 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT12 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT13 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT14 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT15 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>,
<GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST>;
#dma-cells = <1>;
status = "disabled";
};
tegra_axbar: ahub {
compatible = "nvidia,tegra210-axbar";
wakeup-disable;
reg = <0x0 0x702d0800 0x0 0x800>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ahub", "parent", "xbar.ape", "apb2ape";
assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
assigned-clock-rates = <81600000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702d0000 0x0 0x702d0000 0x00010000>;
tegra_admaif: admaif@0x702d0000 {
compatible = "nvidia,tegra210-admaif";
reg = <0x702d0000 0x800>;
dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>, <&adma 4>, <&adma 4>,
<&adma 5>, <&adma 5>, <&adma 6>, <&adma 6>,
<&adma 7>, <&adma 7>, <&adma 8>, <&adma 8>,
<&adma 9>, <&adma 9>, <&adma 10>, <&adma 10>;
dma-names = "rx1", "tx1", "rx2", "tx2", "rx3", "tx3",
"rx4", "tx4", "rx5", "tx5", "rx6", "tx6",
"rx7", "tx7", "rx8", "tx8", "rx9", "tx9",
"rx10", "tx10";
status = "disabled";
};
tegra_sfc1: sfc@702d2000 {
compatible = "nvidia,tegra210-sfc";
reg = <0x702d2000 0x200>;
nvidia,ahub-sfc-id = <0>;
status = "disabled";
};
tegra_sfc2: sfc@702d2200 {
compatible = "nvidia,tegra210-sfc";
reg = <0x702d2200 0x200>;
nvidia,ahub-sfc-id = <1>;
status = "disabled";
};
tegra_sfc3: sfc@702d2400 {
compatible = "nvidia,tegra210-sfc";
reg = <0x702d2400 0x200>;
nvidia,ahub-sfc-id = <2>;
status = "disabled";
};
tegra_sfc4: sfc@702d2600 {
compatible = "nvidia,tegra210-sfc";
reg = <0x702d2600 0x200>;
nvidia,ahub-sfc-id = <3>;
status = "disabled";
};
spkprot@702d8c00 {
compatible = "nvidia,tegra210-spkprot";
reg = <0x702d8c00 0x400>;
nvidia,ahub-spkprot-id = <0>;
status = "disabled";
};
tegra_amixer: amixer@702dbb00 {
compatible = "nvidia,tegra210-amixer";
reg = <0x702dbb00 0x800>;
nvidia,ahub-amixer-id = <0>;
status = "disabled";
};
tegra_i2s1: i2s@702d1000 {
compatible = "nvidia,tegra210-i2s";
reg = <0x702d1000 0x100>;
nvidia,ahub-i2s-id = <0>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_I2S0>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_I2S0_SYNC>,
<&tegra_car TEGRA210_CLK_AUDIO0_MUX>;
clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
"audio_sync";
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
};
tegra_i2s2: i2s@702d1100 {
compatible = "nvidia,tegra210-i2s";
reg = <0x702d1100 0x100>;
nvidia,ahub-i2s-id = <1>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_I2S1>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_I2S1_SYNC>,
<&tegra_car TEGRA210_CLK_AUDIO1_MUX>;
clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
"audio_sync";
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
};
tegra_i2s3: i2s@702d1200 {
compatible = "nvidia,tegra210-i2s";
reg = <0x702d1200 0x100>;
nvidia,ahub-i2s-id = <2>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_I2S2>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_I2S2_SYNC>,
<&tegra_car TEGRA210_CLK_AUDIO2_MUX>;
clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
"audio_sync";
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
};
tegra_i2s4: i2s@702d1300 {
compatible = "nvidia,tegra210-i2s";
reg = <0x702d1300 0x100>;
nvidia,ahub-i2s-id = <3>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_I2S3>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_I2S3_SYNC>,
<&tegra_car TEGRA210_CLK_AUDIO3_MUX>;
clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
"audio_sync";
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
};
tegra_i2s5: i2s@702d1400 {
compatible = "nvidia,tegra210-i2s";
reg = <0x702d1400 0x100>;
nvidia,ahub-i2s-id = <4>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_I2S4>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_I2S4_SYNC>,
<&tegra_car TEGRA210_CLK_AUDIO4_MUX>;
clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
"audio_sync";
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
};
tegra_amx1: amx@702d3000 {
compatible = "nvidia,tegra210-amx";
reg = <0x702d3000 0x100>;
nvidia,ahub-amx-id = <0>;
status = "disabled";
};
tegra_amx2: amx@702d3100 {
compatible = "nvidia,tegra210-amx";
reg = <0x702d3100 0x100>;
nvidia,ahub-amx-id = <1>;
status = "disabled";
};
tegra_adx1: adx@702d3800 {
compatible = "nvidia,tegra210-adx";
reg = <0x702d3800 0x100>;
nvidia,ahub-adx-id = <0>;
status = "disabled";
};
tegra_adx2: adx@702d3900 {
compatible = "nvidia,tegra210-adx";
reg = <0x702d3900 0x100>;
nvidia,ahub-adx-id = <1>;
status = "disabled";
};
tegra_dmic1: dmic@702d4000 {
compatible = "nvidia,tegra210-dmic";
reg = <0x702d4000 0x100>;
nvidia,ahub-dmic-id = <0>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_DMIC1>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
clock-names = "dmic", "parent";
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
};
tegra_dmic2: dmic@702d4100 {
compatible = "nvidia,tegra210-dmic";
reg = <0x702d4100 0x100>;
nvidia,ahub-dmic-id = <1>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_DMIC2>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
clock-names = "dmic", "parent";
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
};
tegra_dmic3: dmic@702d4200 {
compatible = "nvidia,tegra210-dmic";
reg = <0x702d4200 0x100>;
nvidia,ahub-dmic-id = <2>;
status = "disabled";
clocks = <&tegra_car TEGRA210_CLK_DMIC3>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
clock-names = "dmic", "parent";
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
assigned-clock-parents =
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
};
tegra_afc1: afc@702d7000 {
compatible = "nvidia,tegra210-afc";
reg = <0x702d7000 0x100>;
nvidia,ahub-afc-id = <0>;
status = "disabled";
};
tegra_afc2: afc@702d7100 {
compatible = "nvidia,tegra210-afc";
reg = <0x702d7100 0x100>;
nvidia,ahub-afc-id = <1>;
status = "disabled";
};
tegra_afc3: afc@702d7200 {
compatible = "nvidia,tegra210-afc";
reg = <0x702d7200 0x100>;
nvidia,ahub-afc-id = <2>;
status = "disabled";
};
tegra_afc4: afc@702d7300 {
compatible = "nvidia,tegra210-afc";
reg = <0x702d7300 0x100>;
nvidia,ahub-afc-id = <3>;
status = "disabled";
};
tegra_afc5: afc@702d7400 {
compatible = "nvidia,tegra210-afc";
reg = <0x702d7400 0x100>;
nvidia,ahub-afc-id = <4>;
status = "disabled";
};
tegra_afc6: afc@702d7500 {
compatible = "nvidia,tegra210-afc";
reg = <0x702d7500 0x100>;
nvidia,ahub-afc-id = <5>;
status = "disabled";
};
tegra_mvc1: mvc@702da000 {
compatible = "nvidia,tegra210-mvc";
reg = <0x702da000 0x200>;
nvidia,ahub-mvc-id = <0>;
status = "disabled";
};
tegra_mvc2: mvc@702da200 {
compatible = "nvidia,tegra210-mvc";
reg = <0x702da200 0x200>;
nvidia,ahub-mvc-id = <1>;
status = "disabled";
};
tegra_iqc1: iqc@702de000 {
compatible = "nvidia,tegra210-iqc";
reg = <0x702de000 0x200>;
nvidia,ahub-iqc-id = <0>;
status = "disabled";
};
tegra_iqc2: iqc@702de200 {
compatible = "nvidia,tegra210-iqc";
reg = <0x702de200 0x200>;
nvidia,ahub-iqc-id = <1>;
status = "disabled";
};
tegra_ope1: ope@702d8000 {
compatible = "nvidia,tegra210-ope";
reg = <0x702d8000 0x100>,
<0x702d8100 0x100>,
<0x702d8200 0x200>;
nvidia,ahub-ope-id = <0>;
status = "disabled";
};
tegra_ope2: ope@702d8400 {
compatible = "nvidia,tegra210-ope";
reg = <0x702d8400 0x100>,
<0x702d8500 0x100>,
<0x702d8600 0x200>;
nvidia,ahub-ope-id = <1>;
status = "disabled";
};
};
tegra_adsp_audio: adsp_audio {
compatible = "nvidia,tegra210-adsp-audio";
wakeup-disable;
iommus = <&smmu TEGRA_SWGROUP_APE>;
iommu-resv-regions = <0x0 0x0 0x0 0x70300000 0x0 0xFFF00000 0xffffffff 0xffffffff>;
iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
nvidia,adma_ch_start = <11>;
nvidia,adma_ch_cnt = <11>;
interrupt-parent = <&tegra_agic>;
interrupts = <GIC_SPI INT_ADMA_EOT11 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT12 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT13 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT14 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT15 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>,
<GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH
ROUTE_TO_ADSP>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>,
<&tegra_car TEGRA210_CLK_APE>;
clock-names = "ahub", "ape";
status = "disabled";
};
#if TEGRA_AUDIO_BUS_DT_VERSION >= DT_VERSION_2
};
#else
adma@702e2000 {
wakeup-disable;
power-domains = <&pd_audio>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>,
<&tegra_car TEGRA210_CLK_APB2APE>,
<&tegra_car TEGRA210_CLK_APE>;
clock-names = "ahub", "apb2ape", "adma.ape";
};
ahub {
power-domains = <&pd_audio>;
};
adsp_audio {
power-domains = <&adsp_pd>;
};
#endif
hda@70030000 {
compatible = "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
interrupts = <0 81 0x04>;
clocks = <&tegra_car TEGRA210_CLK_HDA>,
<&tegra_car TEGRA210_CLK_HDA2HDMI>,
<&tegra_car TEGRA210_CLK_HDA2CODEC_2X>,
<&tegra_car TEGRA210_CLK_MAUD>;
clock-names = "hda", "hda2hdmi",
"hda2codec_2x", "maud";
status = "disabled";
};
pinmux@700008d4 {
clkreq_0_bi_dir_state: clkreq_0_bi_dir {
clkreq0 {
nvidia,pins = "pex_l0_clkreq_n_pa1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
clkreq_1_bi_dir_state: clkreq_1_bi_dir {
clkreq1 {
nvidia,pins = "pex_l1_clkreq_n_pa4";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
clkreq_0_in_dir_state: clkreq_0_in_dir {
clkreq0 {
nvidia,pins = "pex_l0_clkreq_n_pa1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
clkreq_1_in_dir_state: clkreq_1_in_dir {
clkreq1 {
nvidia,pins = "pex_l1_clkreq_n_pa4";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
};
pcie@1003000 {
compatible = "nvidia,tegra210-pcie", "nvidia,tegra124-pcie";
power-domains = <&pd_pcie>;
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
0x0 0x01003800 0x0 0x00000800 /* AFI registers */
0x0 0x11FFF000 0x0 0x00001000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <0 98 0x04>, /* controller interrupt */
<0 99 0x04>; /* MSI interrupt */
interrupt-names = "intr", "msi";
clocks = <&tegra_car TEGRA210_CLK_PCIE>,
<&tegra_car TEGRA210_CLK_AFI>,
<&tegra_car TEGRA210_CLK_PLL_E>,
<&tegra_car TEGRA210_CLK_CML0>,
<&tegra_car TEGRA210_CLK_MSELECT>;
clock-names = "pex", "afi", "pll_e", "cml", "mselect";
resets = <&tegra_car 70>,
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 0 98 0x04>;
pinctrl-names = "clkreq-0-bi-dir-enable", "clkreq-1-bi-dir-enable",
"clkreq-0-in-dir-enable", "clkreq-1-in-dir-enable",
"pex-io-dpd-dis", "pex-io-dpd-en";
pinctrl-0 = <&clkreq_0_bi_dir_state>;
pinctrl-1 = <&clkreq_1_bi_dir_state>;
pinctrl-2 = <&clkreq_0_in_dir_state>;
pinctrl-3 = <&clkreq_1_in_dir_state>;
pinctrl-4 = <&pex_io_dpd_disable_state>;
pinctrl-5 = <&pex_io_dpd_enable_state>;
iommus = <&smmu TEGRA_SWGROUP_AFI>;
iommu-map = <0x0 &smmu TEGRA_SWGROUP_AFI 0x1000>;
iommu-map-mask = <0x0>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
status = "disabled";
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <4>;
nvidia,afi-ctl-offset = <0x110>;
nvidia,disable-aspm-states = <0xf>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
phys = <&{/xusb_padctl@7009f000/pads/pcie/lanes/pcie-1}>;
#else
phys = <&tegra_padctl_uphy TEGRA_PADCTL_UPHY_PCIE_P(0)>;
#endif
phy-names = "pcie-phy";
};
pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <1>;
nvidia,afi-ctl-offset = <0x118>;
nvidia,disable-aspm-states = <0xf>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
phys = <&{/xusb_padctl@7009f000/pads/pcie/lanes/pcie-0}>;
#else
phys = <&tegra_padctl_uphy TEGRA_PADCTL_UPHY_PCIE_P(1)>;
#endif
phy-names = "pcie-phy";
};
};
i2c1: i2c@7000c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <0 38 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
status = "disabled";
clock-frequency = <400000>;
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_I2C1>, <&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "div-clk", "parent";
resets = <&tegra_car 12>;
reset-names = "i2c";
};
i2c2: i2c@7000c400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <0 84 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
status = "disabled";
clock-frequency = <100000>;
dmas = <&apbdma 22>, <&apbdma 22>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_I2C2>, <&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "div-clk", "parent";
resets = <&tegra_car 54>;
reset-names = "i2c";
};
i2c3: i2c@7000c500 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <0 92 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
status = "disabled";
clock-frequency = <400000>;
dmas = <&apbdma 23>, <&apbdma 23>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_I2C3>, <&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "div-clk", "parent";
resets = <&tegra_car 67>;
reset-names = "i2c";
};
i2c4: i2c@7000c700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <0 120 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
status = "disabled";
clock-frequency = <100000>;
dmas = <&apbdma 26>, <&apbdma 26>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_I2C4>, <&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "div-clk", "parent";
resets = <&tegra_car 103>;
reset-names = "i2c";
};
i2c5: i2c@7000d000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <0 53 0x04>;
scl-gpio = <&gpio 195 0>;
sda-gpio = <&gpio 196 0>;
nvidia,require-cldvfs-clock;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
status = "disabled";
clock-frequency = <400000>;
dmas = <&apbdma 24>, <&apbdma 24>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_I2C5>, <&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "div-clk", "parent";
resets = <&tegra_car 47>;
reset-names = "i2c";
};
i2c6: i2c@7000d100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <0 63 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
status = "disabled";
clock-frequency = <400000>;
dmas = <&apbdma 30>, <&apbdma 30>;
dma-names = "rx", "tx";
clocks = <&tegra_car TEGRA210_CLK_I2C6>, <&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = "div-clk", "parent";
resets = <&tegra_car 166>;
reset-names = "i2c";
};
sdhci3: sdhci@700b0600 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = < 0 31 0x04 >;
aux-device-name = "sdhci-tegra.3";
iommus = <&smmu TEGRA_SWGROUP_SDMMC4A>;
nvidia,runtime-pm-type = <1>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
clock-names = "sdmmc";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
sdhci2: sdhci@700b0400 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = < 0 19 0x04 >;
aux-device-name = "sdhci-tegra.2";
iommus = <&smmu TEGRA_SWGROUP_SDMMC3A>;
nvidia,runtime-pm-type = <0>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
clock-names = "sdmmc";
resets = <&tegra_car 67>;
reset-names = "sdhci";
status = "disabled";
};
sdhci1: sdhci@700b0200 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = < 0 15 0x04 >;
aux-device-name = "sdhci-tegra.1";
nvidia,runtime-pm-type = <1>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
clock-names = "sdmmc";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
sdhci0: sdhci@700b0000 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = < 0 14 0x04 >;
aux-device-name = "sdhci-tegra.0";
iommus = <&smmu TEGRA_SWGROUP_SDMMC1A>;
nvidia,runtime-pm-type = <1>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
clock-names = "sdmmc";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
efuse@7000f800 {
compatible = "nvidia,tegra210-efuse";
reg = <0x0 0x7000f800 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_FUSE>;
clock-names = "fuse";
nvidia,clock-always-on;
status = "disabled";
efuse-burn {
compatible = "nvidia,tegra210-efuse-burn";
clocks = <&tegra_car TEGRA210_CLK_CLK_M>;
clock-names = "clk_m";
status = "disabled";
};
};
actmon@6000c800 {
status = "okay";
mc_all { /* MC_ALL actmon device */
status = "okay";
};
};
kfuse@7000fc00 {
compatible = "nvidia,tegra210-kfuse";
reg = <0x0 0x7000fc00 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_KFUSE>;
clock-names = "kfuse";
status = "okay";
};
pmc-iopower {
compatible = "nvidia,tegra210-pmc-iopower";
pad-controllers = <&tegra_pmc TEGRA_IO_PAD_GROUP_SYS
&tegra_pmc TEGRA_IO_PAD_GROUP_UART
&tegra_pmc TEGRA_IO_PAD_GROUP_AUDIO
&tegra_pmc TEGRA_IO_PAD_GROUP_CAM
&tegra_pmc TEGRA_IO_PAD_GROUP_PEX_CTRL
&tegra_pmc TEGRA_IO_PAD_GROUP_SDMMC1
&tegra_pmc TEGRA_IO_PAD_GROUP_SDMMC3
&tegra_pmc TEGRA_IO_PAD_GROUP_HV
&tegra_pmc TEGRA_IO_PAD_GROUP_AUDIO_HV
&tegra_pmc TEGRA_IO_PAD_GROUP_DBG
&tegra_pmc TEGRA_IO_PAD_GROUP_DMIC
&tegra_pmc TEGRA_IO_PAD_GROUP_GPIO
&tegra_pmc TEGRA_IO_PAD_GROUP_SPI
&tegra_pmc TEGRA_IO_PAD_GROUP_SPI_HV
&tegra_pmc TEGRA_IO_PAD_GROUP_DSI
&tegra_pmc TEGRA_IO_PAD_GROUP_DSIB
&tegra_pmc TEGRA_IO_PAD_GROUP_DSIC
&tegra_pmc TEGRA_IO_PAD_GROUP_DSID
&tegra_pmc TEGRA_IO_PAD_GROUP_HDMI>;
pad-names = "sys", "uart", "audio", "cam", "pex-ctrl",
"sdmmc1", "sdmmc3", "hv", "audio-hv", "debug", "dmic",
"gpio", "spi", "spi-hv", "dsia", "dsib", "dsic", "dsid",
"hdmi";
status = "disabled";
};
dtv@7000c300 {
compatible = "nvidia,tegra210-dtv";
reg = <0x0 0x7000c300 0x0 0x100>;
dmas = <&apbdma 11>;
dma-names = "rx";
status = "disabled";
};
xudc@700d0000 {
compatible = "nvidia,tegra210-xudc";
reg = <0x0 0x700d0000 0x0 0x8000>,
<0x0 0x700d8000 0x0 0x1000>,
<0x0 0x700d9000 0x0 0x1000>;
#if TEGRA_XUSB_PADCONTROL_VERSION >= DT_VERSION_2
interrupts = <0 44 0x4>;
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
<&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>;
nvidia,xusb-padctl = <&xusb_padctl>;
#else
interrupts = <0 44 0x4
0 49 0x4>;
#endif
iommus = <&smmu TEGRA_SWGROUP_XUSB_DEV>;
status = "disabled";
charger-detector = <&tegra_usb_cd>;
};
tegra_mc: memory-controller@70019000 {
compatible = "nvidia,tegra210-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA210_CLK_MC>,
<&tegra_car TEGRA210_CLK_EMC>;
clock-names = "mc", "emc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
status = "disabled";
};
tegra_pwm_dfll: pwm@70110000 {
compatible = "nvidia,tegra210-dfll-pwm";
reg = <0x0 0x70110000 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_REF>;
clock-names = "ref";
pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
#pwm-cells = <2>;
status = "disabled";
};
tegra_clk_dfll: clock@70110000 {
compatible = "nvidia,tegra210-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */
<0 0x70110100 0 0x100>, /* Integrated I2C controller */
<0 0x70110200 0 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA210_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
out-clock-name="dfll_cpu";
status = "disabled";
};
soctherm: soctherm@0x700E2000 {
compatible = "nvidia,tegra-soctherm", "nvidia,tegra210-soctherm";
reg = <0x0 0x700E2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
<0x0 0x60006000 0x0 0x400>, /* 1: CAR reg_base */
<0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
reg-names = "soctherm-reg", "car-reg", "ccroc-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
<&tegra_car TEGRA210_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car TEGRA210_CLK_SOC_THERM>;
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
status = "disabled";
interrupt-controller;
#interrupt-cells = <2>;
soctherm-clock-frequency = <51000000>;
tsensor-clock-frequency = <400000>;
sensor-params-tall = <16300>;
sensor-params-tiddq = <1>;
sensor-params-ten-count = <1>;
sensor-params-tsample = <120>;
sensor-params-pdiv = <8>;
sensor-params-tsamp-ate = <480>;
sensor-params-pdiv-ate = <8>;
hw-pllx-offsets = <TEGRA124_SOCTHERM_SENSOR_CPU 1000 7000
TEGRA124_SOCTHERM_SENSOR_GPU 2000 4000>;
nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
throttle-cfgs {
throttle_heavy: heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-percent = <85>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <2>;
};
};
fuse_war@fuse_rev_0_1 {
device_type = "fuse_war";
match_fuse_rev = <0 1>;
cpu0 = <1088700 397600 >;
cpu1 = <1077600 1073200 >;
cpu2 = <1104800 (-617000) >;
cpu3 = <1093800 (-901200)>;
mem0 = <1085300 (-98400) >;
mem1 = <1104800 (-99000) >;
gpu = <1085800 (-1097500)>;
pllx = <1078800 (-890700)>;
};
fuse_war@fuse_rev_2 {
device_type = "fuse_war";
match_fuse_rev = <2>;
cpu0 = <1085000 3244200 >;
cpu1 = <1126200 (-67500) >;
cpu2 = <1098400 2251100 >;
cpu3 = <1108000 602700>;
mem0 = <1069200 3549900>;
mem1 = <1173700 (-6263600)>;
gpu = <1074300 2734900>;
pllx = <1039700 6829100>;
};
/* throttlectl - hardware 'throttle' devices */
throttle@critical {
device_type = "throttlectl";
cdev-type = "tegra-shutdown";
cooling-min-state = <0>;
cooling-max-state = <3>;
#cooling-cells = <2>;
};
throttle@heavy {
device_type = "throttlectl";
cdev-type = "tegra-heavy";
cooling-min-state = <0>;
cooling-max-state = <3>;
#cooling-cells = <2>;
priority = <100>;
throttle_dev = <&{/soctherm@0x700E2000/throttle_dev@cpu_high}
&{/soctherm@0x700E2000/throttle_dev@gpu_high}>;
};
throttle_dev@cpu_high {
depth = <85>;
};
throttle_dev@gpu_high {
level = "heavy_throttling";
};
};
tegra-aotag {
compatible = "nvidia,tegra21x-aotag";
parent-block = <&{/pmc@7000e400}>;
/*
* interrupts =
* #interrupt-names =
*/
status = "disabled";
sensor-params-tall = <76>;
sensor-params-tiddq = <1>;
sensor-params-ten-count = <16>;
sensor-params-tsample = <9>;
sensor-params-pdiv = <8>;
sensor-params-tsamp-ate = <39>;
sensor-params-pdiv-ate = <8>;
#thermal-sensor-cells = <0>;
/* make this to '1' in case of more than one sensors */
/*
* right way to do with multiple sensors is -
* sensor0 : sensor@<0x.....>
* etc.
* e.g,
* sensor@0 {
* sensor-name = "aotag0";
* sensor-id = <0>;
* };
*
*/
sensor-name = "aotag0";
sensor-id = <0>;
advertised-sensor-id = <9>;
/*
* sensor-type = "nvidia,tegra21x-aotag";
* not required, use 'compatible' instead.
* keeping it as a comment
*/
sensor-nominal-temp-cp = <25>;
sensor-nominal-temp-ft = <105>;
sensor-compensation-a = <10632>;
sensor-compensation-b = <(-67490)>;
};
tegra_cec {
compatible = "nvidia,tegra210-cec";
reg = <0x0 0x70015000 0x0 0x00001000>;
interrupts = <0 3 0x04>;
clocks = <&tegra_car TEGRA210_CLK_CEC>;
clock-names = "cec";
status = "disabled";
};
tegra_watchdog: watchdog@60005100 {
compatible = "nvidia,tegra-wdt-t21x";
reg = <0x0 0x60005100 0x0 0x20 /* WDT0 registers */
0x0 0x60005088 0x0 0x8>; /* TMR0 registers */
interrupts = <0 123 0x04>;
nvidia,expiry-count = <4>;
nvidia,timer-index = <7>;
nvidia,enable-on-init;
status = "disabled";
};
tegra_fiq_debugger {
compatible = "nvidia,fiq-debugger";
use-console-port;
interrupts = <0 123 0x04>; /* WDT_CPU */
};
ptm {
compatible = "nvidia,ptm";
reg = <0x0 0x72010000 0x0 0x1000>, /* funnel_major */
<0x0 0x72030000 0x0 0x1000>, /* etf */
<0x0 0x72040000 0x0 0x1000>, /* replicator */
<0x0 0x72050000 0x0 0x1000>, /* etr */
<0x0 0x72060000 0x0 0x1000>, /* tpiu */
<0x0 0x73010000 0x0 0x1000>, /* funnel_bccplex */
<0x0 0x73440000 0x0 0x1000>, /* ptm0 */
<0x0 0x73540000 0x0 0x1000>, /* ptm1 */
<0x0 0x73640000 0x0 0x1000>, /* ptm2 */
<0x0 0x73740000 0x0 0x1000>, /* ptm3 */
<0x0 0x72820000 0x0 0x1000>, /* funnel_minor */
<0x0 0x72a1c000 0x0 0x1000>; /* ape */
};
mselect {
compatible = "nvidia,tegra-mselect";
interrupts = < 0 175 0x4 >;
reg = < 0x0 0x50060000 0x0 0x1000 >;
status = "disabled";
};
cpuidle {
compatible = "nvidia,tegra210-cpuidle";
cc4-no-retention;
};
apbmisc@70000800 {
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
<0x0 0x70000008 0x0 0x04>; /* Strapping options */
};
nvdumper {
compatible = "nvidia,tegra210-nvdumper";
status = "disabled";
};
tegra-pmc-blink-pwm {
compatible = "nvidia,tegra210-pmc-blink-pwm";
status = "disabled";
};
nvpmodel {
compatible = "nvidia,nvpmodel";
status = "disabled";
};
extcon {
disp-state {
compatible = "extcon-disp-state";
#extcon-cells = <1>;
};
};
};