84 lines
2.5 KiB
Plaintext
84 lines
2.5 KiB
Plaintext
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/*
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* arch/arm64/boot/dts/tegra210-platforms/tegra210-thermal.dtsi
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*
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* Copyright (c) 2014 - 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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thermal-zones {
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AO-therm {
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status = "disabled";
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors = <&{/tegra-aotag}>;
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/* in case of multiple sensors -
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* <&{/tegra-aotag/sensor} [0|1|..]>
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*/
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trips {
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trip_shutdown {
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temperature = <110000>;
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hysteresis = <0>;
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type = "critical";
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writable;
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};
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};
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};
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CPU-therm {
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polling-delay = <0>;
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polling-delay-passive = <500>;
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thermal-sensors = <&{/soctherm@0x700E2000} TEGRA124_SOCTHERM_SENSOR_CPU>;
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status = "disabled";
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};
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GPU-therm {
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polling-delay = <0>;
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polling-delay-passive = <500>;
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thermal-sensors = <&{/soctherm@0x700E2000} TEGRA124_SOCTHERM_SENSOR_GPU>;
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status = "disabled";
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};
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LCPU-therm {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors = <&{/soctherm@0x700E2000} TEGRA124_SOCTHERM_SENSOR_MEM>;
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status = "disabled";
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};
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PLL-therm {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors = <&{/soctherm@0x700E2000} TEGRA124_SOCTHERM_SENSOR_PLLX>;
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status = "disabled";
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};
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};
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core_dvfs_floor: core_dvfs_cdev_floor {
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compatible = "nvidia,tegra-core-cdev-action";
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cdev-type = "CORE-floor";
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#cooling-cells = <2>; /* min followed by max */
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};
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core_dvfs_cap: core_dvfs_cdev_cap {
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compatible = "nvidia,tegra-core-cdev-action";
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cdev-type = "CORE-cap";
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#cooling-cells = <2>; /* min followed by max */
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clocks = <&tegra_car TEGRA210_CLK_CAP_VCORE_C2BUS>,
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<&tegra_car TEGRA210_CLK_CAP_VCORE_C3BUS>,
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<&tegra_car TEGRA210_CLK_CAP_VCORE_SCLK>,
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<&tegra_car TEGRA210_CLK_CAP_VCORE_HOST1X>,
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<&tegra_car TEGRA210_CLK_CAP_VCORE_ABUS>;
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clock-names = "c2bus_cap", "c3bus_cap", "sclk_cap",
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"host1x_cap", "adsp_cap";
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};
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};
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