34 lines
729 B
C
34 lines
729 B
C
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
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/* core clocks */
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#define CLK_FIN_PLL 1
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#define CLK_FOUT_APLL 2
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#define CLK_FOUT_CPLL 3
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#define CLK_FOUT_MPLL 4
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#define CLK_FOUT_BPLL 5
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#define CLK_FOUT_KPLL 6
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_UART0 128
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#define CLK_SCLK_UART1 129
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#define CLK_SCLK_UART2 130
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#define CLK_SCLK_UART3 131
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#define CLK_SCLK_MMC0 132
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#define CLK_SCLK_MMC1 133
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#define CLK_SCLK_MMC2 134
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/* gate clocks */
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#define CLK_UART0 257
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#define CLK_UART1 258
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#define CLK_UART2 259
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#define CLK_UART3 260
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#define CLK_MCT 315
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#define CLK_MMC0 351
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#define CLK_MMC1 352
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#define CLK_MMC2 353
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#define CLK_NR_CLKS 512
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
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