100 lines
3.4 KiB
C
100 lines
3.4 KiB
C
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/*
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* include/dt-bindings/display/tegra-dc.h
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __TEGRA_DC_H
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#define __TEGRA_DC_H
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/* tegra_dc_out.type */
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#define TEGRA_DC_OUT_RGB 0
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#define TEGRA_DC_OUT_HDMI 1
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#define TEGRA_DC_OUT_DSI 2
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#define TEGRA_DC_OUT_DP 3
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#define TEGRA_DC_OUT_LVDS 4
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#define TEGRA_DC_OUT_NVSR_DP 5
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#define TEGRA_DC_OUT_FAKE_DP 6
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#define TEGRA_DC_OUT_FAKE_DSIA 7
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#define TEGRA_DC_OUT_FAKE_DSIB 8
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#define TEGRA_DC_OUT_FAKE_DSI_GANGED 9
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#define TEGRA_DC_OUT_NULL 10
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/* Keep as the last dc_out_define*/
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#define TEGRA_DC_OUT_MAX 11
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/* tegra_dc_out.dither */
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#define TEGRA_DC_UNDEFINED_DITHER 0
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#define TEGRA_DC_DISABLE_DITHER 1
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#define TEGRA_DC_ORDERED_DITHER 2
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#define TEGRA_DC_ERRDIFF_DITHER 3
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#define TEGRA_DC_TEMPORAL_DITHER 4
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/* bits for tegra_dc_out.flags */
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#define TEGRA_DC_OUT_HOTPLUG_HIGH (0 << 1)
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#define TEGRA_DC_OUT_HOTPLUG_LOW (1 << 1)
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#define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON (0 << 2)
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#define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND (1 << 2)
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#define TEGRA_DC_OUT_CONTINUOUS_MODE (0 << 3)
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#define TEGRA_DC_OUT_ONE_SHOT_MODE (1 << 3)
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#define TEGRA_DC_OUT_N_SHOT_MODE (1 << 4)
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#define TEGRA_DC_OUT_ONE_SHOT_LP_MODE (1 << 5)
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#define TEGRA_DC_OUT_INITIALIZED_MODE (1 << 6)
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/* Makes hotplug GPIO a LP0 wakeup source */
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#define TEGRA_DC_OUT_HOTPLUG_WAKE_LP0 (1 << 7)
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/* bots for tegra_dc_out.hdcp_policy */
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#define TEGRA_DC_HDCP_POLICY_ALWAYS_ON 0
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#define TEGRA_DC_HDCP_POLICY_ON_DEMAND 1
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#define TEGRA_DC_HDCP_POLICY_ALWAYS_OFF 2
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/* tegra_dc_out.align */
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#define TEGRA_DC_ALIGN_MSB 0
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#define TEGRA_DC_ALIGN_LSB 1
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/* tegra_dc_out.order */
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#define TEGRA_DC_ORDER_RED_BLUE 0
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#define TEGRA_DC_ORDER_BLUE_RED 1
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/* tegra_fb_data.flags */
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#define TEGRA_FB_FLIP_ON_PROBE (1 << 0)
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/* tegra_dc_platform_data.flags */
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#define TEGRA_DC_FLAG_ENABLED (1 << 0)
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#define TEGRA_DC_FLAG_SET_EARLY_MODE (1 << 1)
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#define TEGRA_DC_FLAG_FBCON_DISABLED (1 << 2)
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/* tegra_dc_out_pin.name */
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#define TEGRA_DC_OUT_PIN_DATA_ENABLE 0
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#define TEGRA_DC_OUT_PIN_H_SYNC 1
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#define TEGRA_DC_OUT_PIN_V_SYNC 2
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#define TEGRA_DC_OUT_PIN_PIXEL_CLOCK 3
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/* tegra_dc_out_pin.pol */
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#define TEGRA_DC_OUT_PIN_POL_LOW 0
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#define TEGRA_DC_OUT_PIN_POL_HIGH 1
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/* tegra_hdmi_out.generic_infoframe_type */
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#define HDMI_INFOFRAME_TYPE_SPD 0x83
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#define HDMI_INFOFRAME_TYPE_HDR 0x87
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#endif /* __TEGRA_DC_H */
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