273 lines
9.2 KiB
C
273 lines
9.2 KiB
C
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/*
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* This header provides constants for binding nvidia,swgroup ID
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*
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* Copyright (c) 2014-2018 NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H
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#define _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H
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#define TEGRA_SWGROUP_INVALID 0xff /* 0x238 */
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#define TEGRA_SWGROUP_AFI 0 /* 0x238 */
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#define TEGRA_SWGROUP_AVPC 1 /* 0x23c */
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#define TEGRA_SWGROUP_DC 2 /* 0x240 */
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#define TEGRA_SWGROUP_DCB 3 /* 0x244 */
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#define TEGRA_SWGROUP_EPP 4 /* 0x248 */
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#define TEGRA_SWGROUP_G2 5 /* 0x24c */
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#define TEGRA_SWGROUP_HC 6 /* 0x250 */
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#define TEGRA_SWGROUP_HDA 7 /* 0x254 */
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#define TEGRA_SWGROUP_ISP 8 /* 0x258 */
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#define TEGRA_SWGROUP_ISP2 8
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#define TEGRA_SWGROUP_DC14 9 /* 0x490 *//* Exceptional non-linear */
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#define TEGRA_SWGROUP_DC12 10 /* 0xa88 *//* Exceptional non-linear */
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#define TEGRA_SWGROUP_MPE 11 /* 0x264 */
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#define TEGRA_SWGROUP_MSENC 11
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#define TEGRA_SWGROUP_NVENC 11
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#define TEGRA_SWGROUP_NV 12 /* 0x268 */
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#define TEGRA_SWGROUP_NV2 13 /* 0x26c */
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#define TEGRA_SWGROUP_PPCS 14 /* 0x270 */
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#define TEGRA_SWGROUP_SATA2 15 /* 0x274 */
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#define TEGRA_SWGROUP_SATA 16 /* 0x278 */
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#define TEGRA_SWGROUP_VDE 17 /* 0x27c */
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#define TEGRA_SWGROUP_VI 18 /* 0x280 */
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#define TEGRA_SWGROUP_VII2C 18 /* 0x280 */
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#define TEGRA_SWGROUP_VIC 19 /* 0x284 */
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#define TEGRA_SWGROUP_XUSB_HOST 20 /* 0x288 */
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#define TEGRA_SWGROUP_XUSB_DEV 21 /* 0x28c */
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#define TEGRA_SWGROUP_A9AVP 22 /* 0x290 */
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#define TEGRA_SWGROUP_TSEC 23 /* 0x294 */
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#define TEGRA_SWGROUP_PPCS1 24 /* 0x298 */
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#define TEGRA_SWGROUP_SDMMC1A 25 /* 0xa94 *//* Linear shift again */
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#define TEGRA_SWGROUP_SDMMC2A 26 /* 0xa98 */
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#define TEGRA_SWGROUP_SDMMC3A 27 /* 0xa9c */
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#define TEGRA_SWGROUP_SDMMC4A 28 /* 0xaa0 */
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#define TEGRA_SWGROUP_ISP2B 29 /* 0xaa4 */
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#define TEGRA_SWGROUP_GPU 30 /* 0xaa8, DO NOT USE THIS */
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#define TEGRA_SWGROUP_GPUB 31 /* 0xaac */
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#define TEGRA_SWGROUP_PPCS2 32 /* 0xab0 */
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#define TEGRA_SWGROUP_NVDEC 33 /* 0xab4 */
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#define TEGRA_SWGROUP_APE 34 /* 0xab8 */
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#define TEGRA_SWGROUP_SE 35 /* 0xabc */
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#define TEGRA_SWGROUP_NVJPG 36 /* 0xac0 */
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#define TEGRA_SWGROUP_HC1 37 /* 0xac4 */
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#define TEGRA_SWGROUP_SE1 38 /* 0xac8 */
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#define TEGRA_SWGROUP_AXIAP 39 /* 0xacc */
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#define TEGRA_SWGROUP_ETR 40 /* 0xad0 */
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#define TEGRA_SWGROUP_TSECB 41 /* 0xad4 */
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#define TEGRA_SWGROUP_TSEC1 42 /* 0xad8 */
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#define TEGRA_SWGROUP_TSECB1 43 /* 0xadc */
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#define TEGRA_SWGROUP_NVDEC1 44 /* 0xae0 */
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/* Reserved 45 */
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#define TEGRA_SWGROUP_AXIS 46 /* 0xae8 */
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#define TEGRA_SWGROUP_EQOS 47 /* 0xaec */
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#define TEGRA_SWGROUP_UFSHC 48 /* 0xaf0 */
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#define TEGRA_SWGROUP_NVDISPLAY 49 /* 0xaf4 */
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#define TEGRA_SWGROUP_BPMP 50 /* 0xaf8 */
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#define TEGRA_SWGROUP_AON 51 /* 0xafc */
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#define TEGRA_SWGROUP_SMMU_TEST 52
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#define TEGRA_SWGROUP_ISP2B1 53 /* 0x808, SE2 on t210b01 */
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/* Reserved 50 */
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#define TWO_U32_OF_U64(x) ((x) & 0xffffffff) ((x) >> 32)
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#define TEGRA_SWGROUP_BIT(x) (1ULL << TEGRA_SWGROUP_##x)
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#define TEGRA_SWGROUP_CELLS(x) TWO_U32_OF_U64(TEGRA_SWGROUP_BIT(x))
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#define TEGRA_SWGROUP_CELLS2(x1, x2) \
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TWO_U32_OF_U64( TEGRA_SWGROUP_BIT(x1) | \
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TEGRA_SWGROUP_BIT(x2))
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#define TEGRA_SWGROUP_CELLS3(x1, x2, x3) \
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TWO_U32_OF_U64( TEGRA_SWGROUP_BIT(x1) | \
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TEGRA_SWGROUP_BIT(x2) | \
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TEGRA_SWGROUP_BIT(x3))
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#define TEGRA_SWGROUP_CELLS4(x1, x2, x3, x4) \
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TWO_U32_OF_U64( TEGRA_SWGROUP_BIT(x1) | \
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TEGRA_SWGROUP_BIT(x2) | \
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TEGRA_SWGROUP_BIT(x3) | \
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TEGRA_SWGROUP_BIT(x4))
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#define TEGRA_SWGROUP_CELLS5(x1, x2, x3, x4, x5) \
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TWO_U32_OF_U64( TEGRA_SWGROUP_BIT(x1) | \
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TEGRA_SWGROUP_BIT(x2) | \
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TEGRA_SWGROUP_BIT(x3) | \
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TEGRA_SWGROUP_BIT(x4) | \
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TEGRA_SWGROUP_BIT(x5))
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#define TEGRA_SWGROUP_CELLS9(x1, x2, x3, x4, x5, x6, x7, x8, x9) \
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TWO_U32_OF_U64( TEGRA_SWGROUP_BIT(x1) | \
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TEGRA_SWGROUP_BIT(x2) | \
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TEGRA_SWGROUP_BIT(x3) | \
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TEGRA_SWGROUP_BIT(x4) | \
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TEGRA_SWGROUP_BIT(x5) | \
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TEGRA_SWGROUP_BIT(x6) | \
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TEGRA_SWGROUP_BIT(x7) | \
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TEGRA_SWGROUP_BIT(x8) | \
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TEGRA_SWGROUP_BIT(x9))
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#define TEGRA_SWGROUP_CELLS12(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12) \
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TWO_U32_OF_U64( TEGRA_SWGROUP_BIT(x1) | \
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TEGRA_SWGROUP_BIT(x2) | \
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TEGRA_SWGROUP_BIT(x3) | \
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TEGRA_SWGROUP_BIT(x4) | \
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TEGRA_SWGROUP_BIT(x5) | \
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TEGRA_SWGROUP_BIT(x6) | \
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TEGRA_SWGROUP_BIT(x7) | \
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TEGRA_SWGROUP_BIT(x8) | \
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TEGRA_SWGROUP_BIT(x9) | \
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TEGRA_SWGROUP_BIT(x10)| \
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TEGRA_SWGROUP_BIT(x11)| \
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TEGRA_SWGROUP_BIT(x12))
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#define TEGRA_SWGROUP_MAX 64
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#define SWGIDS_ERROR_CODE (~0ULL)
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#define swgids_is_error(x) ((x) == SWGIDS_ERROR_CODE)
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/*
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* The above definitions are for the older tegra chips using the Tegra SMMU. For
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* tegra chips using the ARM SMMU the following is used. The notion of bit maps
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* is removed since they are not very scalable.
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*/
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/* Host clients. */
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#define TEGRA_SID_HC 0x1 /* 1 */
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#define TEGRA_SID_VIC 0x3 /* 3 */
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#define TEGRA_SID_VI 0x4 /* 4 */
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#define TEGRA_SID_ISP 0x5 /* 5 */
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#define TEGRA_SID_NVDEC 0x6 /* 6 */
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#define TEGRA_SID_NVENC 0x7 /* 7 */
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#define TEGRA_SID_NVJPG 0x8 /* 8 */
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#define TEGRA_SID_NVDISPLAY 0x9 /* 9 */
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#define TEGRA_SID_TSEC 0xa /* 10 */
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#define TEGRA_SID_TSECB 0xb /* 11 */
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#define TEGRA_SID_SE 0xc /* 12 */
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#define TEGRA_SID_SE1 0xd /* 13 */
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/* GPU clients. */
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#define TEGRA_SID_GPUB 0x10 /* 16 */
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/* Other SoC clients */
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#define TEGRA_SID_AFI 0x11 /* 17 */
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#define TEGRA_SID_HDA 0x12 /* 18 */
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#define TEGRA_SID_ETR 0x13 /* 19 */
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#define TEGRA_SID_EQOS 0x14 /* 20 */
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#define TEGRA_SID_UFSHC 0x15 /* 21 */
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#define TEGRA_SID_AON 0x16 /* 22 */
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#define TEGRA_SID_SDMMC4A 0x17 /* 23 */
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#define TEGRA_SID_SDMMC3A 0x18 /* 24 */
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#define TEGRA_SID_SDMMC2A 0x19 /* 25 */
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#define TEGRA_SID_SDMMC1A 0x1a /* 26 */
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#define TEGRA_SID_XUSB_HOST 0x1b /* 27 */
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#define TEGRA_SID_XUSB_DEV 0x1c /* 28 */
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#define TEGRA_SID_SATA2 0x1d /* 29 */
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#define TEGRA_SID_APE 0x1e /* 30 */
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/*
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* The BPMP has hard coded their SID value in their FW which is not built
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* in the normal Linux tree. As a result, changing the SID requires a
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* considerable amount of work.
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*/
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#define TEGRA_SID_BPMP 0x32 /* 50 */
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/* For smmu tests */
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#define TEGRA_SID_SMMU_TEST 0x33 /* 51 */
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/*
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* This is the t18x specific component of the new SID dt-binding.
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*/
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#define TEGRA_SID_NVCSI 0x2 /* 2 */
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#define TEGRA_SID_SE2 0xe /* 14 */
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#define TEGRA_SID_SE3 0xf /* 15 */
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#define TEGRA_SID_SCE 0x1f /* 31 */
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/* The GPC DMA clients. */
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#define TEGRA_SID_GPCDMA_0 0x20 /* 32 */
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#define TEGRA_SID_GPCDMA_1 0x21 /* 33 */
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#define TEGRA_SID_GPCDMA_2 0x22 /* 34 */
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#define TEGRA_SID_GPCDMA_3 0x23 /* 35 */
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#define TEGRA_SID_GPCDMA_4 0x24 /* 36 */
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#define TEGRA_SID_GPCDMA_5 0x25 /* 37 */
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#define TEGRA_SID_GPCDMA_6 0x26 /* 38 */
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#define TEGRA_SID_GPCDMA_7 0x27 /* 39 */
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/* The APE DMA Clients. */
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#define TEGRA_SID_APE_1 0x28 /* 40 */
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#define TEGRA_SID_APE_2 0x29 /* 41 */
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/* The Camera RTCPU. */
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#define TEGRA_SID_RCE 0x2a /* 42 */
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/* The Camera RTCPU on Host1x address space. */
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#define TEGRA_SID_RCE_1X 0x2b /* 43 */
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/* The APE DMA Clients. */
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#define TEGRA_SID_APE_3 0x2c /* 44 */
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/* The Camera RTCPU running on APE */
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#define TEGRA_SID_APE_CAM 0x2d /* 45 */
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#define TEGRA_SID_APE_CAM_1X 0x2e /* 46 */
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/* Host1x virtualization clients. */
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#define TEGRA_SID_HOST1X_CTX0 0x38 /* 56 */
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#define TEGRA_SID_HOST1X_CTX1 0x39 /* 57 */
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#define TEGRA_SID_HOST1X_CTX2 0x3a /* 58 */
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#define TEGRA_SID_HOST1X_CTX3 0x3b /* 59 */
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#define TEGRA_SID_HOST1X_CTX4 0x3c /* 60 */
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#define TEGRA_SID_HOST1X_CTX5 0x3d /* 61 */
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#define TEGRA_SID_HOST1X_CTX6 0x3e /* 62 */
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#define TEGRA_SID_HOST1X_CTX7 0x3f /* 63 */
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/* Host1x command buffers */
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#define TEGRA_SID_HC_VM0 0x40
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#define TEGRA_SID_HC_VM1 0x41
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#define TEGRA_SID_HC_VM2 0x42
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#define TEGRA_SID_HC_VM3 0x43
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#define TEGRA_SID_HC_VM4 0x44
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#define TEGRA_SID_HC_VM5 0x45
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#define TEGRA_SID_HC_VM6 0x46
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#define TEGRA_SID_HC_VM7 0x47
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/* SE data buffers */
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#define TEGRA_SID_SE_VM0 0x48
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#define TEGRA_SID_SE_VM1 0x49
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#define TEGRA_SID_SE_VM2 0x4a
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#define TEGRA_SID_SE_VM3 0x4b
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#define TEGRA_SID_SE_VM4 0x4c
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#define TEGRA_SID_SE_VM5 0x4d
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#define TEGRA_SID_SE_VM6 0x4e
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#define TEGRA_SID_SE_VM7 0x4f
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/* XUSB virtual functions */
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#define TEGRA_SID_XUSB_VF0 0x5d
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#define TEGRA_SID_XUSB_VF1 0x5e
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#define TEGRA_SID_XUSB_VF2 0x5f
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#define TEGRA_SID_XUSB_VF3 0x60
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/* Special clients */
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#define TEGRA_SID_PASSTHROUGH 0x7f
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#define TEGRA_SID_INVALID 0x0
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/*
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* These macros will be removed once the bitmap problem is sorted out. Until
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* then this is equivalent to TEGRA_SWGROUP_CELLS() only with TEGRA_SID_*
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* instead of TEGRA_SWGROUP_*.
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*/
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#define TEGRA_SID(x) (TEGRA_SID_ ## x)
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/*
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* These are unique id's that the IOMMU uses to put different
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* devices into the same IOMMU group and shared address space
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* Add this to a devices iommu-group-id property
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*/
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#define TEGRA_IOMMU_GROUP_HOST1X 0x1
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#define TEGRA_IOMMU_GROUP_APE 0x2
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#define TEGRA_IOMMU_GROUP_RTCPU 0x3
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#define TEGRA_IOMMU_GROUP_SE 0x4
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#endif /* _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H */
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