86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
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/*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
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#ifdef TEGRA_SWGROUP_USE_UPSTREAM
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_AFI 3
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#define TEGRA_SWGROUP_AVPC 4
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#define TEGRA_SWGROUP_HDA 5
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#define TEGRA_SWGROUP_HC 6
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#define TEGRA_SWGROUP_NVENC 7
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#define TEGRA_SWGROUP_PPCS 8
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#define TEGRA_SWGROUP_SATA 9
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#define TEGRA_SWGROUP_MPCORE 10
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#define TEGRA_SWGROUP_ISP2 11
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#define TEGRA_SWGROUP_XUSB_HOST 12
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#define TEGRA_SWGROUP_XUSB_DEV 13
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#define TEGRA_SWGROUP_ISP2B 14
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#define TEGRA_SWGROUP_TSEC 15
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#define TEGRA_SWGROUP_A9AVP 16
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#define TEGRA_SWGROUP_GPU 17
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#define TEGRA_SWGROUP_SDMMC1A 18
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#define TEGRA_SWGROUP_SDMMC2A 19
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#define TEGRA_SWGROUP_SDMMC3A 20
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#define TEGRA_SWGROUP_SDMMC4A 21
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#define TEGRA_SWGROUP_VIC 22
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#define TEGRA_SWGROUP_VI 23
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#define TEGRA_SWGROUP_NVDEC 24
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#define TEGRA_SWGROUP_APE 25
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#define TEGRA_SWGROUP_NVJPG 26
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#define TEGRA_SWGROUP_SE 27
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#define TEGRA_SWGROUP_AXIAP 28
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#define TEGRA_SWGROUP_ETR 29
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#define TEGRA_SWGROUP_TSECB 30
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#endif /* TEGRA_SWGROUP_USE_UPSTREAM */
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#define TEGRA210_MC_RESET_AFI 0
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#define TEGRA210_MC_RESET_AVPC 1
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#define TEGRA210_MC_RESET_DC 2
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#define TEGRA210_MC_RESET_DCB 3
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#define TEGRA210_MC_RESET_HC 4
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#define TEGRA210_MC_RESET_HDA 5
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#define TEGRA210_MC_RESET_ISP2 6
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#define TEGRA210_MC_RESET_MPCORE 7
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#define TEGRA210_MC_RESET_NVENC 8
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#define TEGRA210_MC_RESET_PPCS 9
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#define TEGRA210_MC_RESET_SATA 10
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#define TEGRA210_MC_RESET_VI 11
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#define TEGRA210_MC_RESET_VIC 12
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#define TEGRA210_MC_RESET_XUSB_HOST 13
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#define TEGRA210_MC_RESET_XUSB_DEV 14
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#define TEGRA210_MC_RESET_A9AVP 15
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#define TEGRA210_MC_RESET_TSEC 16
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#define TEGRA210_MC_RESET_SDMMC1 17
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#define TEGRA210_MC_RESET_SDMMC2 18
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#define TEGRA210_MC_RESET_SDMMC3 19
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#define TEGRA210_MC_RESET_SDMMC4 20
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#define TEGRA210_MC_RESET_ISP2B 21
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#define TEGRA210_MC_RESET_GPU 22
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#define TEGRA210_MC_RESET_NVDEC 23
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#define TEGRA210_MC_RESET_APE 24
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#define TEGRA210_MC_RESET_SE 25
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#define TEGRA210_MC_RESET_NVJPG 26
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#define TEGRA210_MC_RESET_AXIAP 27
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#define TEGRA210_MC_RESET_ETR 28
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#define TEGRA210_MC_RESET_TSECB 29
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#endif
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