157 lines
6.5 KiB
Plaintext
157 lines
6.5 KiB
Plaintext
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* Device tree binding for Nvidia Tegra18x cpufreq driver for EDVD device
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--------------------------------------------
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This document defines the device-specific binding for the Tegra18x cpufreq
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driver. It should not contain bindings for generic tegra cpufreq driver
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which are common across all the tegra cpufreq platform driver.
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The Tegra18x cpufreq driver adjusts CPU frequency by writing voltage and
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freq hint in EDVD per core volt freq request registers. It calculates per
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core cpufreq by reading per core cycle counters. Cycles are measured by
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reading EDVD per core clock count registers and divided by ref clock counter.
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The ressult is multiplied by ref clock.
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Tegra18x cpufreq driver considers these EDVD registers as device to measure
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and adjust cpu freq. There is one instance of EDVD for the Denver cluster
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and one for the A57 cluster.
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Required properties:
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- compatible: should be "nvidia,tegra18x-cpufreq".
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- reg: an array of four 64-bit unsigned integers.
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the base address and size for Denver EDVD aperture and the base
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address and size for the A57 EDVD aperture.
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- status: "okay" or "disabled" to enable/disable the node.
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Optional properties:
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- freq_table_step_size:
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Cpu frequency table step size. If not provided, default value 4.
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For example, if list of original available frequencies(in KHz) are:
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345600 384000 422400 460800 499200 537600 576000 614400 652800 691200
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729600 768000 806400 844800 883200 921600 960000 998400 1036800 1075200
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1113600 1152000 1190400 1228800 1267200 1305600 1344000 1382400 1420800
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1459200 1497600 1536000 1574400 1612800 1651200 1689600 1728000 1766400
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1804800 1843200
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Setting freq_table_step_size to 1 will include all these frequencies in
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cpufreq table as available frequencies.
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Setting freq_table_step_size to 2 will skip alternative entries and will
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include remaining entries in cpufreq table as available frequencies.
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With freq_table_step_size as 2, cpufreq table available frequencies will be:
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345600 422400 499200 576000 652800 729600 806400 883200 960000 1036800
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1113600 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000
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1804800 1843200
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Similarly, freq_table_step_size of value 3 will skip every 2nd and 3rd entries
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in groups of 3 entries consecutively.
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- nvidia,enable-autocc3: Enable auto_cc3.
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Auto cc3 is the idle state where freq request is not considered for the cpus
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in WFI/WFE. It has per cluster, <cluster_no enable/disable> entries to enable
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/ disable per cluster cc3.
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It assumes that 0th index of the array as entry for 0th(M_CLUSTER)
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cluster. It should be set as <cluster_no and enable/disable> way.
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Therfore 1nd index is considered as enable/disable value for
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0th cluster. Like that 2nd index will have entry for 1st(B_cluster)
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cluster 3rd index will have enable/disable value for 1st cluster.
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Assumptions -
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clusters values -
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0 - M_CLUSTER
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1 - B_CLUSTER
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Disable/Enable
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0 - Disable
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1 - Enable
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* Need to fill all the clusters state.
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* If a cluster is disabled its cc3 freq will be Don't care.
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- nvidia,autocc3-freq: autocc3 cluster freq.
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If a cluster goes in idle, cc3 freq will be requested for the cluster.
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It has per cluster values to request per cluster cc3 freq.
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It takes values as <cluster_no freq_in_khz>. It assumes 0th index of
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the array has entry of 0th(M_CLUSTER) cluster, 1st index as 0th cluster
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cc3 freq, 2nd index as 1st(B_CLUSTER) cluster and 3rd index as 1st
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cluster cc3 freq.
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Assumptions -
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clusters values -
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0 - M_CLUSTER
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1 - B_CLUSTER
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freq_in_khz values -
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0 - Fmin@Vmin
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freq_khz - cc3 freq for the cluster
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* Need to fill all the clusters state.
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* If a cluster is disabled its cc3 freq will be Don't care.
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Example 1:
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----------
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cpufreq@e070000 {
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compatible = "nvidia,tegra18x-cpufreq";
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reg = <0x0 0x0e070000 0x0 0x1000>, /* M/Denver cluster */
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<0x0 0x0e060000 0x0 0x1000>; /* B/ARM cluster */
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status = "disabled";
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};
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Example 2:
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----------
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cpufreq@e070000 {
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compatible = "nvidia,tegra18x-cpufreq";
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reg = <0x0 0x0e070000 0x0 0x1000>, /* M/Denver cluster */
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<0x0 0x0e060000 0x0 0x1000>; /* B/ARM cluster */
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freq_table_step_size = /bits/ 16 <1>;
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};
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Example 3: cpufreq and auto-cc3 enabled, freq = Fmax@Vmin for each cluster
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----------
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cpufreq@e070000 {
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compatible = "nvidia,tegra18x-cpufreq";
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reg = <0x0 0x0e070000 0x0 0x1000>, /* M/Denver cluster */
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<0x0 0x0e060000 0x0 0x1000>; /* B/ARM cluster */
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status = "okay";
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nvidia,enable-autocc3 = <0 1>, /* M_CLUSTER Enable*/
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<1 1>; /* B_CLUSTER Enable*/
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nvidia,autocc3-freq = <0 0>, /* M_CLUSTER Fmin@vmin*/
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<1 0>; /* B_CLUSTER Fmin@vmin*/
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};
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Example 4: cpufreq and auto-cc3 enabled, cc3_freq for both cluster
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----------
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cpufreq@e070000 {
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compatible = "nvidia,tegra18x-cpufreq";
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reg = <0x0 0x0e070000 0x0 0x1000>, /* M/Denver cluster */
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<0x0 0x0e060000 0x0 0x1000>; /* B/ARM cluster */
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status = "okay";
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nvidia,enable-autocc3 = <0 0>, /* M_CLUSTER Disable*/
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<1 1>; /* B_CLUSTER Enable*/
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nvidia,autocc3-freq = <0 0>, /* M_CLUSTER Fmin@vmin*/
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<1 0>; /* B_CLUSTER Fmin@vmin*/
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};
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Example 5: cpufreq and auto-cc3 enabled, cc3_freq for M cluster
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auto-cc3 is disabled for B cluster
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----------
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cpufreq@e070000 {
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compatible = "nvidia,tegra18x-cpufreq";
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reg = <0x0 0x0e070000 0x0 0x1000>, /* M/Denver cluster */
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<0x0 0x0e060000 0x0 0x1000>; /* B/ARM cluster */
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status = "okay";
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nvidia,enable-autocc3 = <0 0>, /* M_CLUSTER Enable*/
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<1 0>; /* B_CLUSTER Disable*/
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};
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Example 6: cpufreq and auto-cc3 enabled, freq = Fmax@Vmin for M cluster
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auto-cc3 is disabled for B cluster
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----------
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cpufreq@e070000 {
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compatible = "nvidia,tegra18x-cpufreq";
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reg = <0x0 0x0e070000 0x0 0x1000>, /* M/Denver cluster */
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<0x0 0x0e060000 0x0 0x1000>; /* B/ARM cluster */
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status = "okay";
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nvidia,enable-autocc3 = <0 1>, /* M_CLUSTER Enable*/
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<1 1>; /* B_CLUSTER Enable*/
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nvidia,autocc3-freq = <0 512000>, /* M_CLUSTER 512Mhz*/
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<1 644000>; /* B_CLUSTER 644 Mhz*/
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};
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