140 lines
6.4 KiB
Plaintext
140 lines
6.4 KiB
Plaintext
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* Nvidia sdhci-tegra controller
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This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci-tegra driver.
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Required properties:
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- compatible: Should be "nvidia,tegra186-sdhci"
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- reg: Specify start address and registers count details
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- interrupts: Specify the interrupts IRQ info for device
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Optional properties:
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- tap-delay: Specify number of cycles to delay for reading data from device
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- nvidia,ddr-tap-delay: Specify number of cycles to delay for reading data from device in ddr mode.
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- trim-delay: Specify number of cycles to delay for writing data to device
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- ddr-trim-delay: Specify number of cycles to delay for writing data to device when in DDR mode
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- dqs-trim-delay: HS400 Tap value for incoming DQS path trimmer.
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- dqs-trim-delay-hs533: HS533 Tap value for incoming DQS path trimmer.
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- max-clk-limit: Specify the maximum clock limit for the device
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- ddr-clk-limit: Specify the maximum clock frequency in kHz for device in DDR mode
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- mmc-ocr-mask: Specify OCR register masking details. Based on this value the power up voltage depending on board capabilities can be selected.
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- uhs-mask: Specify modes that are masked for the device
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Mask HS200 mode: 0x20
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Mask HS400 mode: 0x40
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Mask SDR104 mode: 0x10
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Mask SDR50 mode: 0x4
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Mask DDR50 mode: 0x8
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- calib-3v3-offsets and calib-1v8-offsets: Specify caliberation settings at 3.3V and at 1.8V
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- compad-vref-3v3 and compad-vref-1v8: used to control Vref_sel input of calibration pad. Should be set based on pads used for controller before starting pad drive strength calibration.
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- power-gpios: details of GPIO port used to power up SDIO card
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- default-drv-type: Drive strength to select for SDIO devices is encoded as 8-bit char as follows
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Drive strength Type B: 0x0
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Drive strength Type A: 0x1
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Drive strength Type C: 0x2
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Drive strength Type D: 0x3
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- nvidia,update-pinctrl-settings: Specify desired pin control settings if different from default pin control settings done during init.
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- pwr-off-during-lp0: Some devices like SDIO devices may use this to select power off mode when in LP0 or deep sleep or SC7 state.
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- power-off-rail: flag when set enables sdmmc reboot notifier
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- nvidia,dll-calib-needed: DLL calibration is needed for SDMMC4 and SDMMC2 devices if they are enumerated
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- pwrdet-support: flag when set indicates the sdmmc controller instance needs power detect bit programming for voltage switching.
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in HS400 mode.
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- nvidia,disable-auto-cal: This flag when set will disable auto calibration
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- nvidia,en-io-trim-volt: Enable IO trimmer voltage
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- nvidia,is-emmc: Enable this flag for eMMC devices
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- nvidia,sd-device: Enable this flag for SD devices
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- nvidia,limit-vddio-max-volt: enable this flag for sdmmc1/3 if it has Vddio 3.3v support.
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- nvidia,enable-hs533-mode: Set this Flag toenable HS533 mode.
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---> eMMC card does not advertise HS533 mode support in device registers.
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---> This flag has to be enabled only if the card supports HS533 mode, other wise the consequences are un-known.(Errors will be seen)
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- fixed-clock-freq: The first element is for ID mode. The rest of the entries are for different modes indexed as per ios timings.
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ID MODE 0
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MMC_TIMING_LEGACY 1
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MMC_TIMING_MMC_HS 2
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MMC_TIMING_SD_HS 3
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MMC_TIMING_UHS_SDR12 4
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MMC_TIMING_UHS_SDR25 5
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MMC_TIMING_UHS_SDR50 6
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MMC_TIMING_UHS_SDR104 7
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MMC_TIMING_UHS_DDR50 8
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MMC_TIMING_MMC_HS200 9
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MMC_TIMING_MMC_HS400 10
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- nvidia,auto-cal-slew-override: flag to set AUTO_CAL_SLW_OVERRIDE bit in SDMMC_AUTO_CAL_CONFIG_0 register.
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- nvidia,enable-cq: Set this flag to enable CQ.
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- nvidia,enable-hwcq: Enable this flag to select hardware CQ support available on selected Tegra chips.
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- nvidia,enable-strobe-mode: Enable enhance strobe mode when eMMC device runs at HS400 mode.
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- nvidia,en-periodic-calib: Enable periodic calibration support for sdmmc1/sdmmc3. Auto calibration sequence will be run at interval of 100ms during sdmmc1/sdmmc3 interfaces are active.
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- nvidia,adma3-enable: boolean property to enable ADMA3 for the sdhci controller instance if supported by the Tegra chip.
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- nvidia,en-32bit-bc: Enables 32 bit block count support on sdhci controller, if HW supports.
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- nvidia,en-periodic-cflush: Enables periodic cache flush for sdmmc device to improve performance. This check is not required for
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SD and SDIO devices since they do not have volatile cache memory. So, set it only for eMMC device when required.
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- nvidia,periodic-cflush-to: Sets the periodic cache flush timeout value.
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- force-non-removable-rescan: Enable to force rescan/reinit for non-removable devices.
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Example:
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sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x3460000 0x0 0x210>;
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interrupts = < 0 65 0x04>;
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max-clk-limit = <200000000>;
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ddr-clk-limit = <48000000>;
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tap-delay = <9>;
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nvidia,ddr-tap-delay = <9>;
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trim-delay = <5>;
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ddr-trim-delay = <5>;
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dqs-trim-delay = <63>;
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dqs-trim-delay-hs533 = <40>;
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mmc-ocr-mask = <0>;
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uhs-mask = <0x60>;
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calib-3v3-offsets = <0x0505>;
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calib-1v8-offsets = <0x0505>;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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nvidia,enable-hs533-mode;
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nvidia,limit-vddio-max-volt;
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nvidia,en-io-trim-volt;
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nvidia,disable-auto-cal;
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pwrdet-support;
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nvidia,dll-calib-needed;
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pwr-off-during-lp0;
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nvidia,enable-strobe-mode;
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nvidia,en-periodic-calib;
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nvidia,enable-cq;
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nvidia,enable-hwcq;
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nvidia,is-emmc;
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nvidia,auto-cal-slew-override;
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nvidia,update-pinctrl-settings;
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pinctrl-names = "sdmmc_schmitt_enable", "sdmmc_schmitt_disable", "sdmmc_clk_schmitt_enable", "sdmmc_clk_schmitt_disable";
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pinctrl-0 = <&sdmmc3_schmitt_enable_state>;
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pinctrl-1 = <&sdmmc3_schmitt_disable_state>;
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pinctrl-2 = <&sdmmc3_clk_schmitt_enable_state>;
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pinctrl-3 = <&sdmmc3_clk_schmitt_disable_state>;
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pll_source = "pll_p", "pll_c4_out2";
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resets = <&tegra_car TEGRA186_RESET_SDMMC4>;
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reset-names = "sdmmc";
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clocks = <&tegra_car TEGRA186_CLK_SDMMC4>,
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<&tegra_car TEGRA186_CLK_PLLP_GRTTA>,
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<&tegra_car TEGRA186_CLK_PLLC4_OUT2>;
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clock-names = "sdmmc4", "pll_p", "pll_c4_out2";
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nvidia,clk-name = "sdmmc4";
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fixed-clock-freq = <25500000 25500000 24000000 47000000 24000000 47000000 94000000 204000000 0 0 0>;
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};
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sdhci@3420000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x3460000 0x0 0x210>;
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interrupts = < 0 65 0x04>;
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power-off-rail;
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cd-gpios = <&tegra_gpio TEGRA_GPIO(P, 5) 0>;
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power-gpios = <180>;
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default-drv-type = <1>;
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nvidia,clk-name = "sdmmc2";
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nvidia,adma3-enable;
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nvidia,sd-device;
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force-non-removable-rescan;
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};
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