94 lines
3.6 KiB
Plaintext
94 lines
3.6 KiB
Plaintext
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Bosch MTTCAN controller Device Tree Bindings
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-------------------------------------------------
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Required properties:
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- compatible : Should be "bosch,mttcan" for M_TTCAN controllers
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- reg : physical base address and size of the M_TTCAN
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registers map, glue logic register maps and
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Message RAM
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- reg-names : Should be "can-regs", "glue-regs" and "msg_ram"
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- interrupts : Should be the interrupt number of M_TTCAN interrupt,
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line 0 and line 1 can have different interrupts.
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- clocks : Clocks used by controller, should be CAN clock,
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CAN host clock and parent PLL.
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- clock-names : Should contain "can", "can_host" and parent PLL.
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- pll_source : Names corresponding parent PLL
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- resets : reset number corresponding to controller reset line.
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- reset-names : Name corresponding to controller reset line.
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- gpio_can_stb : GPIO number and active level to program PHY chip
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- gpio_can_en : GPIO number and active level to enable PHY chip
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- mram-params : Message RAM configuration data.
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Multiple M_TTCAN controller instance can share same
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Message RAM. Location and number of elements per
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category are configurable. Care should be taken while
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configuring Message RAM as the memory overlap is not
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detected and result are unpredictable behaviour.
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The format should be as follows:
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<offset num_sidf_elems num_xidf_elems num_rxf0_elems
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num_rxf1_elems num_rxb_elems num_txe_elems
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num_txb_elems num_tmc_elems>
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The 'offset' is an address offset of the Message RAM
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where the following elements start from.
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M_TTCAN includes the following elements according to
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user manual:
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11-bit Filter 0-128 elements / 0-128 words
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29-bit Filter 0-64 elements / 0-128 words
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Rx FIFO 0 0-64 elements / 0-1152 words
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Rx FIFO 1 0-64 elements / 0-1152 words
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Rx Buffers 0-64 elements / 0-1152 words
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Tx Event FIFO 0-32 elements / 0-64 words
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Tx Buffers 0-32 elements / 0-576 words
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Trigger Memory 0-64 elements / 0-128 words
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Please refer to 2.4.1 Message RAM Configuration in
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Bosch M_TTCAN user manual for details.
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- tx-config : Tx Buffer region configuration. Tx Buffers can be
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in sub configured as Tx Buffers, Tx Queue and TxFIFO.
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Valid configuration are
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* Tx Buffers + Tx Queue
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* Tx Buffers + Tx FIFO
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The format should be as follows
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<num_tx_buf, num_txq, q_mode, tx_max_data_size>
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'num_tx_buf' is number of elements configures as
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buffers. 'num_txq' is number of elements which are
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configured in Queue/FIFO. 'q_mode' to 1 select mode
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as queue, 0 to select FIFO mode. 'tx_max_data_size'
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is max payload of a message. M_TTCAN support 64 bytes
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max payload. 'tx_max_data_size' is used optimize
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Message RAM usage.
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- rx-config : Size of Rx elements max payload.
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The format should be as follow
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<rx_buf_payload, rx_fifo0_payload, rx_fif1_payload>
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Example:
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SoC dtsi:
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mttcan0: mttcan@c310000 {
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compatible = "bosch,mttcan";
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reg = <0x00 0x0c310000 0x00 0x400>,
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<0x00 0x0c311000 0x00 0x32>,
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<0x00 0x0c312000 0x00 0x1000>;
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reg-names = "can-regs", "glue-regs", "msg-ram";
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interrupts = <0 40 0x04 >;
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pll_source = "pllaon";
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clocks = <&tegra_car TEGRA186_CLK_CAN1>,
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<&tegra_car TEGRA186_CLK_CAN1_HOST>,
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<&tegra_car TEGRA186_CLK_PLLAON>;
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clock-names = "can","can_host","pllaon";
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resets = <&tegra_car TEGRA186_RESET_CAN1>;
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reset-names = "can";
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status = "disabled";
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};
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Board dts:
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mttcan@c310000 {
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gpio_can_stb = <&tegra_gpio TEGRA_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
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gpio_can_en = <&tegra_gpio TEGRA_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
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mram-params = <0 16 16 8 8 8 16 16 16>;
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tx-config = <8 8 0 64>;
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rx-config = <64 64 64>;
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status = "okay";
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};
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