140 lines
5.6 KiB
Plaintext
140 lines
5.6 KiB
Plaintext
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NVIDIA Tegra PCIe controller-End Point mode (Synopsys DesignWare Core based)
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This PCIe controller working in end point mode is based on the Synopsis
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Designware PCIe IP
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Required properties:
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- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie-ep".
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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- reg-names: Must include the following entries:
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"appl": Controller's application logic registers
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"window1": First address space aperture window available for PCIe controller
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"config": configuration space region (either window1 or window2 can be used
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for mapping. But in this case, window1 is used)
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"atu_dma": iATU and DMA register (either window1 or window2 can be used
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for mapping. But in this case, window1 is used)
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"window2": Second address space aperture window available for PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The Tegra interrupt that is asserted for controller interrupts
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- core_clk
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- core_apb_rst
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- core_rst
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- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane. Note that the number
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of entries does not have to (though usually will) be equal to the specified
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number of lanes in XBAR configuration. Entries are of the form
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"pcie-p2u-N": where N ranges from 0 to the value specified in xbar config
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- nvidia,pex-rst-gpio: Specify GPIO for PCIe reset signal, see gpio binding
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- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
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- Controller dependent register offsets
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- nvidia,margin-port-cap: MARGIN_PORT_CAP_STATUS reg offset
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0x190 - C4
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0x194 - C0 and C5
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- nvidia,cfg-link-cap-l1sub: L1SUB_CAP_L1SUB reg offset
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0x1b0 - C4
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0x1c4 - C0 and C5
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- nvidia,event-cntr-ctrl: EVENT_COUNTER_CONTROL reg offset
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0x1c4 - C4
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0x1d8 - C0 and C5
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- nvidia,event-cntr-data: EVENT_COUNTER_DATA reg offset
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0x1c8 - C4
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0x1dc - C0 and C5
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- nvidia,margin-lane-cntrl: MARGIN_LANE_CNTRL_STATUS reg offset
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0x184 - C1, C2 and C3
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0x194 - C4
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0x198 - C0 and C5
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- nvidia,device-id: Controller specific PCIe Device-ID
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0x1AD4 - C0
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0x1AD5 - C4
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0x1AD4 - C5
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- nvidia,controller-id : Controller specific ID
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0x0 - C0
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0x4 - C4
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0x5 - C5
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- num-lanes: Must contain an entry to represent number of lanes
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controller is given to get the link up
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Optional properties:
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- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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- nvidia,max-speed: limits controllers max speed to this value.
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1 - Gen-1
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2 - Gen-2
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3 - Gen-3
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4 - Gen-4
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- nvidia,disable-aspm-states : controls advertisement of ASPM states
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bit-0 to '1' : disables advertisement of ASPM-L0s
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bit-1 to '1' : disables advertisement of ASPM-L1. This also disables
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advertisement of ASPM-L1.1 and ASPM-L1.2
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bit-2 to '1' : disables advertisement of ASPM-L1.1
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bit-3 to '1' : disables advertisement of ASPM-L1.2
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- nvidia,update_fc_fixup : needs it to improve perf when a platform is designed
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in such a way that it satisfies at least one of the following conditions
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1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
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2. If C0/C4/C5 operate at their respective max link widths and
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a) speed is Gen-2 and MPS is 256B
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b) speed is >= Gen-3 with any MPS
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- nvidia,bar0-size: Size of BAR-0 through which memory gets exposed to host
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- "nvidia,tsa-config" : Add TSA configuration register address to configure MC
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with production settings for PCIe. Note:- this is applicable only for C5
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- "nvidia,mods" : Add to indicate NVidia specific MODs configuration
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- nvidia,enable-srns: This property needs to be present if the platform has SRNS
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(Separate Reference clocks with No Spread-spectrum clocking) configuration
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implemented. This property initializes PLLs with the internal clock source.
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- nvidia,enable-slot-supplies: This property needs to be present if the
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slots that are owned by controllers operating in the endpoint mode need to be
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supplied with slot power.
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Power supplies for Tegra194:
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//TODO
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Examples:
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=========
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Tegra194:
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--------
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SoC DTSI:
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pcie_c1_ep {
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compatible = "nvidia,tegra194-pcie-ep";
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reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x30040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
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reg-names = "appl", "config", "atu_dma";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_1>;
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clock-names = "core_clk";
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resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_1_APB>,
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<&bpmp_resets TEGRA194_RESET_PEX0_CORE_1>;
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reset-names = "core_apb_rst", "core_rst";
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interrupts = <0 45 0x04>; /* controller interrupt */
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interrupt-names = "intr";
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iommus = <&smmu TEGRA_SID_PCIE1>;
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dma-coherent;
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};
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Board DTS:
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//TODO
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