217 lines
8.6 KiB
Plaintext
217 lines
8.6 KiB
Plaintext
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NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie".
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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- reg-names: Must include the following entries:
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"appl": Controller's application logic registers
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"config": configuration space region
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"atu_dma": iATU and DMA register
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The Tegra interrupt that is asserted for controller interrupts
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"msi": The Tegra interrupt that is asserted when an MSI is received
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- bus-range: Range of bus numbers associated with this controller
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- #address-cells: Address representation for root ports (must be 3)
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- cell 0 specifies the bus and device numbers of the root port:
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[23:16]: bus number
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[15:11]: device number
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- cell 1 denotes the upper 32 address bits and should be 0
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- cell 2 contains the lower 32 address bits and is used to translate to the
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CPU address space
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- #size-cells: Size representation for root ports (must be 2)
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- ranges: Describes the translation of addresses for root ports and standard
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PCI regions. The entries must be 6 cells each, where the first three cells
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correspond to the address as described for the #address-cells property
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above, the fourth cell is the physical CPU address to translate to and the
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fifth and six cells are as described for the #size-cells property above.
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- Entries setup the mapping for the standard I/O, memory and
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prefetchable PCI regions. The first cell determines the type of region
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that is setup:
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- 0x81000000: I/O memory region
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- 0x82000000: non-prefetchable memory region
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- 0xc2000000: prefetchable memory region
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- #interrupt-cells: Size representation for interrupts (must be 1)
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- core_clk
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- core_apb_rst
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- core_rst
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- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane. Note that the number
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of entries does not have to (though usually will) be equal to the specified
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number of lanes in XBAR configuration. Entries are of the form
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"pcie-p2u-N": where N ranges from 0 to the value specified in xbar config
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- Controller dependent register offsets
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- nvidia,cfg-link-cap-l1sub: L1SUB_CAP_L1SUB reg offset
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0x154 - FPGA
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0x194 - C1, C2 and C3
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0x1b0 - C4
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0x1c4 - C0 and C5
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- nvidia,cap-pl16g-status: PL16G_CAP_PL16G_STATUS reg offset
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0x164 - C1, C2 and C3
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0x174 - C4
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0x174 - C0 and C5
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- nvidia,event-cntr-ctrl: EVENT_COUNTER_CONTROL reg offset
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0x168 - FPGA
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0x1a8 - C1, C2 and C3
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0x1c4 - C4
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0x1d8 - C0 and C5
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- nvidia,event-cntr-data: EVENT_COUNTER_DATA reg offset
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0x16c - FPGA
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0x1ac - C1, C2 and C3
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0x1c8 - C4
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0x1dc - C0 and C5
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- nvidia,cap_pl16g_cap_off: CAP_PL16G_CAP_OFF reg offset
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0x178 - C1, C2 and C3
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0x188 - C4
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0x188 - C0 and C5
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- nvidia,margin-port-cap: MARGIN_PORT_CAP_STATUS reg offset
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0x180 - C1, C2 and C3
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0x190 - C4
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0x194 - C0 and C5
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- nvidia,margin-lane-cntrl: MARGIN_LANE_CNTRL_STATUS reg offset
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0x184 - C1, C2 and C3
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0x194 - C4
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0x198 - C0 and C5
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- nvidia,dl-feature-cap: DATA_LINK_FEATURE_CAP reg offset
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0x2dc - C1, C2 and C3
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0x2f8 - C4
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0x30c - C5
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- nvidia,controller-id : Controller specific ID
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0x0 - C0
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0x1 - C1
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0x2 - C2
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0x3 - C3
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0x4 - C4
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0x5 - C5
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- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
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Optional properties:
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- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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- nvidia,max-speed: limits controllers max speed to this value.
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1 - Gen-1
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2 - Gen-2
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3 - Gen-3
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4 - Gen-4
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- nvidia,init-speed: limits controllers init speed to this value.
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1 - Gen-1
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2 - Gen-2
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3 - Gen-3
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4 - Gen-4
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- nvidia,disable-aspm-states : controls advertisement of ASPM states
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bit-0 to '1' : disables advertisement of ASPM-L0s
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bit-1 to '1' : disables advertisement of ASPM-L1. This also disables
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advertisement of ASPM-L1.1 and ASPM-L1.2
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bit-2 to '1' : disables advertisement of ASPM-L1.1
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bit-3 to '1' : disables advertisement of ASPM-L1.2
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- nvidia,disable-clock-request : gives a hint to driver that there is no
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CLKREQ signal routing on board
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- nvidia,enable-fmon : gives a hint to driver that this a safety enabled
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platform
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- nvidia,update_fc_fixup : needs it to improve perf when a platform is designed
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in such a way that it satisfies at least one of the following conditions
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1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
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2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
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a) speed is Gen-2 and MPS is 256B
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b) speed is >= Gen-3 with any MPS
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- nvidia,cdm_check : Enables CDM checking. For more information, refer synopsis
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data book
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- nvidia,enable-power-down : Enables power down of respective controller and
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corresponding PLLs if they are not shared by any other entity
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- "nvidia,pex-wake" : Add PEX_WAKE gpio number to provide wake support.
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- "nvidia,tsa-config" : Add TSA configuration register address to configure MC
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with production settings for PCIe. Note:- this is applicable only for C5
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- "nvidia,dma-poll" : Add this property to do polling instead of interrupt
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mechanism during DMA operation. DMA polling will give accurate perf
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numbers
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- "nvidia,dma-size" : Add this property to provide DMA size input, size will
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set to 1 MB if this property is missing
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- "nvidia,disable-l1-cpm" : Add this property to disable ASPM L1-CPM for the
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immediate end point
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- "nvidia,plat-gpios" : Add gpio number that needs to be configured before
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system goes for enumeration
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- nvidia,enable-srns: This property needs to be present if the platform has SRNS
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(Separate Reference clocks with No Spread-spectrum clocking) configuration
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implemented. This property disables REFCLK supply to EP.
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Power supplies for Tegra194:
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//TODO
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Examples:
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=========
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Tegra194:
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--------
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SoC DTSI:
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pcie_c1_rp {
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compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x30040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
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reg-names = "appl", "config", "atu_dma";
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <1>;
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clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_1>;
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clock-names = "core_clk";
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resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_1_APB>,
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<&bpmp_resets TEGRA194_RESET_PEX0_CORE_1>;
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reset-names = "core_apb_rst", "core_rst";
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interrupts = <0 45 0x04>, /* controller interrupt */
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<0 46 0x04>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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iommus = <&smmu TEGRA_SID_PCIE1>;
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dma-coherent;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc 0 45 0x04>;
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nvidia,max-speed = <2>;
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nvidia,disable-aspm-states = <0x0>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
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0x82000000 0x0 0x30200000 0x0 0x30200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
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0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x40000000>; /* prefetchable memory (1GB) */
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nvidia,cfg-link-cap-l1sub = <0x1c4>;
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nvidia,cap-pl16g-status = <0x174>;
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nvidia,event-cntr-ctrl = <0x1d8>;
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nvidia,event-cntr-data = <0x1dc>;
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};
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Board DTS:
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//TODO
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