92 lines
3.4 KiB
Plaintext
92 lines
3.4 KiB
Plaintext
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NVIDIA Tegra SPE/AON aux CPU, with communication via the "IVC" IPC protocol.
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AON is an aux CPU which communicates with CCPLEX over IVC.
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The AON FW implements IVC, and uses HSP shared mailbox IRQs as part of IVC
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notification. The AON FW expects AST regions 0/1 are already set up for the
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AON to access SYSRAM and GSC carveout in DRAM. It configures the AST region
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2 to point at DRAM IVC carveout upon receiving the carveout address and size
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from CCPLEX.
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* Carveout address: SMMU IOVA of the IPC region
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* Slave address: Some hard coded location that SPE FW knows. Ex: 0x80000000
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== AON top-level node ==
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The AON core is represented by the top-level node.
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Required properties:
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- compatible: Should be "nvidia,tegra186-aon" for T18x.
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- reg: Address entry of AON shared semaphore.
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- nvidia,hsp-shared-mailbox: <HSP-phandle mailbox-number>
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* HSP is a set of HW synchronization primitives used in Tegra to allow
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multiple processors to share resources and communicate together.
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* hsp-shared-mailbox property points to shared mailbox pair used for
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IVC notification.
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* HSP-phandle points to the Tegra HSP platform device.
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* mailbox-number refers to the consumer side mailbox. The producer side
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mailbox is the other one in the same (even-odd) pair.
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Ex: consumer_mbox = 2; producer_mbox = (consumer_mbox ^ 1);
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A HSP irq notification allows a set of source agents in Tegra to request
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the attention of specified target agent. In general the agents are
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processors and irq is used as part of an IPC protocol notification.
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* For more HSP details, refer: ./tegra-hsp.txt.
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- nvidia,ivc-carveout-base-ss: property holds the hsp shared semaphore index
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used to send the ivc carveout base address to the AON fw.
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- nvidia,ivc-carveout-size-ss: property holds the hsp shared semaphore index
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used to send the ivc carveout size to the AON fw.
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- nvidia,ivc-dbg-enable-ss: property holds the hsp shared semaphore index
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used to send the ivc channel id for debug to the AON fw.
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- nvidia,ivc-notify-ss: property holds the hsp shared semaphore index used
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to send the ivc channels that are to be notified.
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Mailbox controller properties:
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- #mbox-cells
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Should be set to <1>.
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The IVC channels are represented as mailbox channels.
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Hence, this binding makes use of the mailbox binding at ../../mailbox/mailbox.txt.
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SMMU properties:
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- #stream-id-cells
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Should be set to <1>.
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This property is used to configure the SMMU to SPE IVC carveout in DRAM.
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== AON sub nodes ==
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* ivc-channels
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Contains a sub-node for each IVC channel implemented by the AON.
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For IVC channel details, please refer: ./tegra-ivc-channel.txt
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Possible example:
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aon: aon@c160000 {
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compatible = "nvidia,tegra186-aon";
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reg = <0x0 0x0c1a0000 0x0 0x20000>; /* AON shared semaphore */
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#mbox-cells = <1>;
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#stream-id-cells = <1>;
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iommus = <&smmu TEGRA_SID_AON>;
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nvidia,hsp-shared-mailbox = <&aon_hsp 2>;
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nvidia,hsp-shared-mailbox-names = "ivc-pair";
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nvidia,ivc-carveout-base-ss = <0>;
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nvidia,ivc-carveout-size-ss = <1>;
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nvidia,ivc-notify-ss = <1>;
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nvidia,ivc-dbg-enable-ss = <0>;
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ivc-channels@80000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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ivc_aon_echo@0 {
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reg = <0x0000>, <0x1000>;
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reg-names = "rx", "tx";
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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ivc_aon_aondbg@480 {
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reg = <0x0480>, <0x1480>;
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reg-names = "rx", "tx";
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nvidia,frame-count = <2>;
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nvidia,frame-size = <128>;
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};
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};
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};
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