47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
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/*
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* IOMMU API for ARM architected SMMU implementations.
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*
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* Copyright (c) 2018 NVIDIA Corporation. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software and related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef _ARM_SMMU_REGS_T19X_H
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#define _ARM_SMMU_REGS_T19X_H
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#include "arm-smmu-regs.h"
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/* SMMU global address space */
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#undef ARM_SMMU_GR0
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#define ARM_SMMU_GR0(smmu) ((smmu)->base[0])
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#undef ARM_SMMU_GR1
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#define ARM_SMMU_GR1(smmu) ((smmu)->base[0] + (1 << (smmu)->pgshift))
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#undef ARM_SMMU_PME
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#define ARM_SMMU_PME(smmu) ((smmu)->base[0] + (3 << (smmu)->pgshift))
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/*
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* SMMU global address space with conditional offset to access secure
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* aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
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* nsGFSYNR0: 0x450)
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*/
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#undef ARM_SMMU_GR0_NS
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#define ARM_SMMU_GR0_NS(smmu) \
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((smmu)->base[0] + \
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((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
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? 0x400 : 0))
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/* Translation context bank */
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#undef ARM_SMMU_CB_BASE
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#define ARM_SMMU_CB_BASE(smmu) ((smmu)->base[0] + ((smmu)->size >> 1))
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#undef ARM_SMMU_CB
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#define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
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#endif /* _ARM_SMMU_REGS_H */
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