255 lines
6.5 KiB
C
255 lines
6.5 KiB
C
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/*
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* Copyright (c) 2018 NVIDIA Corporation. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software and related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_iommu.h>
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#include <linux/of_platform.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/syscore_ops.h>
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#include "arm-smmu-regs-t19x.h"
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#ifdef CONFIG_PM_SLEEP
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#define SMMU_GNSR1_CBAR_CFG(n, smmu_pgshift) \
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((1U << smmu_pgshift) + ARM_SMMU_GR1_CBAR(n))
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#define SMMU_GNSR1_CBA2R_CFG(n, smmu_pgshift) \
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((1U << smmu_pgshift) + ARM_SMMU_GR1_CBA2R(n))
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#define SMMU_CB_CFG(name, n, smmu_size, smmu_pgshift) \
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((smmu_size >> 1) + (n * (1 << smmu_pgshift)) \
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+ ARM_SMMU_CB_ ## name)
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#define SMMU_REG_TABLE_START_REG 0xCAFE05C7U
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#define SMMU_REG_TABLE_END_REG 0xFFFFFFFFU
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#define SMMU_REG_TABLE_END_VALUE 0xFFFFFFFFU
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struct arm_smmu_reg {
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u32 reg;
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u32 val;
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};
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struct arm_smmu_context {
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struct arm_smmu_reg *reg_list;
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phys_addr_t reg_list_pa;
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size_t reg_list_table_size;
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size_t reg_list_mem_size;
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void __iomem **smmu_base;
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u32 *smmu_base_pa;
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unsigned long smmu_size;
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unsigned long smmu_pgshift;
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size_t num_smmus;
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void __iomem *scratch_va;
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} arm_smmu_ctx;
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static phys_addr_t arm_smmu_alloc_reg_list(void)
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{
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unsigned int order = arm_smmu_ctx.reg_list_mem_size >> PAGE_SHIFT;
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struct page *pages = alloc_pages(GFP_KERNEL, order);
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if (!pages)
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return 0;
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return page_to_phys(pages);
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}
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static void arm_smmu_free_reg_list(void)
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{
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unsigned int order = arm_smmu_ctx.reg_list_mem_size >> PAGE_SHIFT;
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struct page *pages = phys_to_page(arm_smmu_ctx.reg_list_pa);
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__free_pages(pages, order);
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}
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static int reg_table_index;
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static void reg_table_set(u32 reg, u32 val)
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{
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arm_smmu_ctx.reg_list[reg_table_index].reg = reg;
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arm_smmu_ctx.reg_list[reg_table_index++].val = val;
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}
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static void context_save_reg(u32 reg)
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{
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u32 reg_paddr, i;
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void __iomem *reg_addr;
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for (i = 0; i < arm_smmu_ctx.num_smmus; i++) {
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reg_addr = arm_smmu_ctx.smmu_base[i] + reg;
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reg_paddr = arm_smmu_ctx.smmu_base_pa[i] + reg;
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reg_table_set(reg_paddr, readl_relaxed(reg_addr));
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}
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}
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#define SMMU_REG_TABLE_START_SIZE 1
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static void context_save_start(void)
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{
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reg_table_index = 0;
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reg_table_set(SMMU_REG_TABLE_START_REG,
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arm_smmu_ctx.reg_list_table_size - 1);
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}
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#define SMMU_REG_TABLE_END_SIZE 1
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static void context_save_end(void)
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{
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reg_table_set(SMMU_REG_TABLE_END_REG, SMMU_REG_TABLE_END_REG);
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}
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#define GNSR_GROUP_REG_SIZE 3
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static void context_save_gnsr0_group(void)
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{
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context_save_reg(ARM_SMMU_GR0_sCR0);
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context_save_reg(ARM_SMMU_GR0_sCR2);
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context_save_reg(ARM_SMMU_GR0_sACR);
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}
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#define SMRG_GROUP_REG_SIZE 2
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static void context_save_smrg_group(int group_num)
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{
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context_save_reg(ARM_SMMU_GR0_SMR(group_num));
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context_save_reg(ARM_SMMU_GR0_S2CR(group_num));
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}
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#define CBAR_GROUP_REG_SIZE 2
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static void context_save_cbar_group(int group_num)
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{
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context_save_reg(SMMU_GNSR1_CBAR_CFG(group_num,
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arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_GNSR1_CBA2R_CFG(group_num,
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arm_smmu_ctx.smmu_pgshift));
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}
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#define CB_GROUP_REG_SIZE 9
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static void context_save_cb_group(int group_num)
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{
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context_save_reg(SMMU_CB_CFG(SCTLR, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(TTBCR2, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(TTBR0_LO, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(TTBR0_HI, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(TTBR1_LO, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(TTBR1_HI, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(TTBCR, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(CONTEXTIDR, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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context_save_reg(SMMU_CB_CFG(S1_MAIR0, group_num,
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arm_smmu_ctx.smmu_size, arm_smmu_ctx.smmu_pgshift));
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}
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#define CB_GROUP_MAX 64
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#define SMRG_GROUP_MAX 128
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#define CBAR_GROUP_MAX 64
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static int arm_smmu_syscore_suspend(void)
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{
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int i;
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context_save_start();
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context_save_gnsr0_group();
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for (i = 0; i < SMRG_GROUP_MAX; i++)
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context_save_smrg_group(i);
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for (i = 0; i < CBAR_GROUP_MAX; i++)
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context_save_cbar_group(i);
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for (i = 0; i < CB_GROUP_MAX; i++)
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context_save_cb_group(i);
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context_save_end();
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return 0;
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}
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static struct syscore_ops arm_smmu_syscore_ops = {
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.suspend = arm_smmu_syscore_suspend,
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};
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int arm_smmu_suspend_init(void __iomem **smmu_base, u32 *smmu_base_pa,
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int num_smmus, unsigned long smmu_size,
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unsigned long smmu_pgshift, u32 scratch_reg_pa)
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{
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int ret = 0;
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arm_smmu_ctx.reg_list_table_size =
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(SMMU_REG_TABLE_START_SIZE + SMMU_REG_TABLE_END_SIZE
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+ (GNSR_GROUP_REG_SIZE
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+ (CB_GROUP_REG_SIZE * CB_GROUP_MAX)
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+ (SMRG_GROUP_REG_SIZE * SMRG_GROUP_MAX)
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+ (CBAR_GROUP_REG_SIZE * CBAR_GROUP_MAX)
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) * num_smmus);
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arm_smmu_ctx.reg_list_mem_size =
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PAGE_ALIGN(arm_smmu_ctx.reg_list_table_size *
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sizeof(struct arm_smmu_reg));
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arm_smmu_ctx.reg_list_pa = arm_smmu_alloc_reg_list();
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if (!arm_smmu_ctx.reg_list_pa) {
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pr_err("Failed to alloc smmu_context memory\n");
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return -ENOMEM;
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}
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arm_smmu_ctx.reg_list = memremap(arm_smmu_ctx.reg_list_pa,
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arm_smmu_ctx.reg_list_mem_size, MEMREMAP_WB);
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if (!arm_smmu_ctx.reg_list) {
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pr_err("Failed to memremap smmu_context\n");
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goto free_reg_list;
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}
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arm_smmu_ctx.scratch_va = ioremap_nocache(scratch_reg_pa, 4);
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if (IS_ERR(arm_smmu_ctx.scratch_va)) {
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pr_err("Failed to ioremap scratch register\n");
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ret = PTR_ERR(arm_smmu_ctx.scratch_va);
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goto unmap_reg_list;
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}
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writel(arm_smmu_ctx.reg_list_pa >> 12, arm_smmu_ctx.scratch_va);
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arm_smmu_ctx.smmu_base_pa = smmu_base_pa;
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arm_smmu_ctx.smmu_base = smmu_base;
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arm_smmu_ctx.smmu_size = smmu_size;
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arm_smmu_ctx.smmu_pgshift = smmu_pgshift;
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arm_smmu_ctx.num_smmus = num_smmus;
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register_syscore_ops(&arm_smmu_syscore_ops);
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return 0;
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unmap_reg_list:
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memunmap(arm_smmu_ctx.reg_list);
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free_reg_list:
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arm_smmu_free_reg_list();
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return ret;
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}
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void arm_smmu_suspend_exit(void)
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{
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if (arm_smmu_ctx.reg_list)
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memunmap(arm_smmu_ctx.reg_list);
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if (arm_smmu_ctx.reg_list_pa)
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arm_smmu_free_reg_list();
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}
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#endif
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