222 lines
6.8 KiB
C
222 lines
6.8 KiB
C
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/*
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* Broadcom PCIE
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* Software-specific definitions shared between device and host side
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* Explains the shared area between host and dongle
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* Copyright (C) 1999-2015, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* $Id: bcmpcie.h 497456 2014-08-19 15:06:33Z $
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*/
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#ifndef _bcmpcie_h_
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#define _bcmpcie_h_
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#include <bcmutils.h>
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#define ADDR_64(x) (x.addr)
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#define HIGH_ADDR_32(x) ((uint32) (((sh_addr_t) x).high_addr))
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#define LOW_ADDR_32(x) ((uint32) (((sh_addr_t) x).low_addr))
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typedef struct {
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uint32 low_addr;
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uint32 high_addr;
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} sh_addr_t;
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#ifdef BCMPCIE_SUPPORT_TX_PUSH_RING
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#define BCMPCIE_PUSH_TX_RING 1
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#else
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#define BCMPCIE_PUSH_TX_RING 0
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#endif /* BCMPCIE_SUPPORT_TX_PUSH_RING */
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/* May be overridden by 43xxxxx-roml.mk */
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#if !defined(BCMPCIE_MAX_TX_FLOWS)
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#define BCMPCIE_MAX_TX_FLOWS 40
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#endif /* ! BCMPCIE_MAX_TX_FLOWS */
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#define PCIE_SHARED_VERSION 0x00005
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#define PCIE_SHARED_VERSION_MASK 0x000FF
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#define PCIE_SHARED_ASSERT_BUILT 0x00100
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#define PCIE_SHARED_ASSERT 0x00200
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#define PCIE_SHARED_TRAP 0x00400
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#define PCIE_SHARED_IN_BRPT 0x00800
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#define PCIE_SHARED_SET_BRPT 0x01000
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#define PCIE_SHARED_PENDING_BRPT 0x02000
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#define PCIE_SHARED_TXPUSH_SPRT 0x04000
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#define PCIE_SHARED_EVT_SEQNUM 0x08000
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#define PCIE_SHARED_DMA_INDEX 0x10000
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/* D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM */
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#define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000
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#define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000
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#define PCIE_SHARED_D2H_SYNC_MODE_MASK \
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(PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM)
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#define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0
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#define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1
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#define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2
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#define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3
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#define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4
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#define BCMPCIE_COMMON_MSGRING_MAX_ID 4
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/* Added only for single tx ring */
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#define BCMPCIE_H2D_TXFLOWRINGID 5
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#define BCMPCIE_H2D_COMMON_MSGRINGS 2
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#define BCMPCIE_D2H_COMMON_MSGRINGS 3
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#define BCMPCIE_COMMON_MSGRINGS 5
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enum h2dring_idx {
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BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = 0,
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BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = 1,
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BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = 2
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};
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enum d2hring_idx {
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BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = 0,
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BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = 1,
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BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = 2
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};
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typedef struct ring_mem {
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uint16 idx;
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uint8 type;
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uint8 rsvd;
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uint16 max_item;
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uint16 len_items;
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sh_addr_t base_addr;
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} ring_mem_t;
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#define RINGSTATE_INITED 1
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typedef struct ring_state {
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uint8 idx;
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uint8 state;
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uint16 r_offset;
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uint16 w_offset;
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uint16 e_offset;
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} ring_state_t;
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typedef struct ring_info {
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/* locations in the TCM where the ringmem is and ringstate are defined */
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uint32 ringmem_ptr; /* ring mem location in TCM */
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uint32 h2d_w_idx_ptr;
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uint32 h2d_r_idx_ptr;
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uint32 d2h_w_idx_ptr;
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uint32 d2h_r_idx_ptr;
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/* host locations where the DMA of read/write indices are */
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sh_addr_t h2d_w_idx_hostaddr;
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sh_addr_t h2d_r_idx_hostaddr;
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sh_addr_t d2h_w_idx_hostaddr;
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sh_addr_t d2h_r_idx_hostaddr;
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uint16 max_sub_queues;
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uint16 rsvd;
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} ring_info_t;
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typedef struct {
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/* shared area version captured at flags 7:0 */
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uint32 flags;
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uint32 trap_addr;
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uint32 assert_exp_addr;
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uint32 assert_file_addr;
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uint32 assert_line;
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uint32 console_addr; /* Address of hnd_cons_t */
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uint32 msgtrace_addr;
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uint32 fwid;
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/* Used for debug/flow control */
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uint16 total_lfrag_pkt_cnt;
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uint16 max_host_rxbufs; /* rsvd in spec */
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uint32 dma_rxoffset; /* rsvd in spec */
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/* these will be used for sleep request/ack, d3 req/ack */
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uint32 h2d_mb_data_ptr;
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uint32 d2h_mb_data_ptr;
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/* information pertinent to host IPC/msgbuf channels */
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/* location in the TCM memory which has the ring_info */
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uint32 rings_info_ptr;
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/* block of host memory for the scratch buffer */
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uint32 host_dma_scratch_buffer_len;
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sh_addr_t host_dma_scratch_buffer;
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/* block of host memory for the dongle to push the status into */
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uint32 device_rings_stsblk_len;
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sh_addr_t device_rings_stsblk;
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#ifdef BCM_BUZZZ
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uint32 buzzz; /* BUZZZ state format strings and trace buffer */
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#endif
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} pciedev_shared_t;
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/* H2D mail box Data */
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#define H2D_HOST_D3_INFORM 0x00000001
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#define H2D_HOST_DS_ACK 0x00000002
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#define H2D_HOST_CONS_INT 0x80000000 /* h2d int for console cmds */
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/* D2H mail box Data */
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#define D2H_DEV_D3_ACK 0x00000001
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#define D2H_DEV_DS_ENTER_REQ 0x00000002
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#define D2H_DEV_DS_EXIT_NOTE 0x00000004
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#define D2H_DEV_FWHALT 0x10000000
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extern pciedev_shared_t pciedev_shared;
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#define NEXTTXP(i, d) ((((i)+1) >= (d)) ? 0 : ((i)+1))
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#define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w)))
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#define NTXPAVAIL(r, w, d) (((d) - NTXPACTIVE((r), (w), (d))) > 1)
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/* Function can be used to notify host of FW halt */
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#define READ_AVAIL_SPACE(w, r, d) \
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((w >= r) ? (w - r) : (d - r))
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#define WRT_PEND(x) ((x)->wr_pending)
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#define DNGL_RING_WPTR(msgbuf) (*((msgbuf)->tcm_rs_w_ptr))
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#define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a))
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#define DNGL_RING_RPTR(msgbuf) (*((msgbuf)->tcm_rs_r_ptr))
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#define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a))
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#define RING_READ_PTR(x) ((x)->ringstate->r_offset)
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#define RING_WRITE_PTR(x) ((x)->ringstate->w_offset)
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#define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr)
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#define RING_MAX_ITEM(x) ((x)->ringmem->max_item)
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#define RING_LEN_ITEMS(x) ((x)->ringmem->len_items)
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#define HOST_RING_BASE(x) ((x)->ring_base.va)
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#define HOST_RING_END(x) ((uint8 *)HOST_RING_BASE((x)) + \
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((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x))))
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#define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w))
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#define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1)
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#define CHECK_WRITE_SPACE(r, w, d) \
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MIN(WRITE_SPACE_AVAIL(r, w, d), WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d))
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#endif /* _bcmpcie_h_ */
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