405 lines
11 KiB
C
405 lines
11 KiB
C
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/*
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* Broadcom AMBA Interconnect definitions.
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*
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* Portions of this code are copyright (c) 2017 Cypress Semiconductor Corporation
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: aidmp.h 514727 2014-11-12 03:02:48Z $
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*/
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#ifndef _AIDMP_H
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#define _AIDMP_H
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/* Manufacturer Ids */
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#define MFGID_ARM 0x43b
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#define MFGID_BRCM 0x4bf
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#define MFGID_MIPS 0x4a7
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/* Component Classes */
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#define CC_SIM 0
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#define CC_EROM 1
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#define CC_CORESIGHT 9
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#define CC_VERIF 0xb
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#define CC_OPTIMO 0xd
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#define CC_GEN 0xe
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#define CC_PRIMECELL 0xf
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/* Enumeration ROM registers */
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#define ER_EROMENTRY 0x000
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#define ER_REMAPCONTROL 0xe00
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#define ER_REMAPSELECT 0xe04
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#define ER_MASTERSELECT 0xe10
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#define ER_ITCR 0xf00
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#define ER_ITIP 0xf04
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/* Erom entries */
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#define ER_TAG 0xe
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#define ER_TAG1 0x6
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#define ER_VALID 1
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#define ER_CI 0
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#define ER_MP 2
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#define ER_ADD 4
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#define ER_END 0xe
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#define ER_BAD 0xffffffff
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#define ER_SZ_MAX 4096 /* 4KB */
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/* EROM CompIdentA */
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#define CIA_MFG_MASK 0xfff00000
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#define CIA_MFG_SHIFT 20
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#define CIA_CID_MASK 0x000fff00
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#define CIA_CID_SHIFT 8
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#define CIA_CCL_MASK 0x000000f0
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#define CIA_CCL_SHIFT 4
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/* EROM CompIdentB */
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#define CIB_REV_MASK 0xff000000
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#define CIB_REV_SHIFT 24
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#define CIB_NSW_MASK 0x00f80000
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#define CIB_NSW_SHIFT 19
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#define CIB_NMW_MASK 0x0007c000
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#define CIB_NMW_SHIFT 14
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#define CIB_NSP_MASK 0x00003e00
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#define CIB_NSP_SHIFT 9
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#define CIB_NMP_MASK 0x000001f0
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#define CIB_NMP_SHIFT 4
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/* EROM MasterPortDesc */
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#define MPD_MUI_MASK 0x0000ff00
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#define MPD_MUI_SHIFT 8
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#define MPD_MP_MASK 0x000000f0
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#define MPD_MP_SHIFT 4
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/* EROM AddrDesc */
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#define AD_ADDR_MASK 0xfffff000
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#define AD_SP_MASK 0x00000f00
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#define AD_SP_SHIFT 8
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#define AD_ST_MASK 0x000000c0
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#define AD_ST_SHIFT 6
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#define AD_ST_SLAVE 0x00000000
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#define AD_ST_BRIDGE 0x00000040
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#define AD_ST_SWRAP 0x00000080
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#define AD_ST_MWRAP 0x000000c0
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#define AD_SZ_MASK 0x00000030
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#define AD_SZ_SHIFT 4
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#define AD_SZ_4K 0x00000000
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#define AD_SZ_8K 0x00000010
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#define AD_SZ_16K 0x00000020
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#define AD_SZ_SZD 0x00000030
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#define AD_AG32 0x00000008
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#define AD_ADDR_ALIGN 0x00000fff
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#define AD_SZ_BASE 0x00001000 /* 4KB */
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/* EROM SizeDesc */
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#define SD_SZ_MASK 0xfffff000
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#define SD_SG32 0x00000008
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#define SD_SZ_ALIGN 0x00000fff
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#if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
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typedef volatile struct _aidmp {
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uint32 oobselina30; /* 0x000 */
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uint32 oobselina74; /* 0x004 */
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uint32 PAD[6];
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uint32 oobselinb30; /* 0x020 */
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uint32 oobselinb74; /* 0x024 */
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uint32 PAD[6];
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uint32 oobselinc30; /* 0x040 */
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uint32 oobselinc74; /* 0x044 */
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uint32 PAD[6];
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uint32 oobselind30; /* 0x060 */
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uint32 oobselind74; /* 0x064 */
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uint32 PAD[38];
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uint32 oobselouta30; /* 0x100 */
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uint32 oobselouta74; /* 0x104 */
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uint32 PAD[6];
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uint32 oobseloutb30; /* 0x120 */
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uint32 oobseloutb74; /* 0x124 */
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uint32 PAD[6];
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uint32 oobseloutc30; /* 0x140 */
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uint32 oobseloutc74; /* 0x144 */
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uint32 PAD[6];
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uint32 oobseloutd30; /* 0x160 */
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uint32 oobseloutd74; /* 0x164 */
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uint32 PAD[38];
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uint32 oobsynca; /* 0x200 */
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uint32 oobseloutaen; /* 0x204 */
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uint32 PAD[6];
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uint32 oobsyncb; /* 0x220 */
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uint32 oobseloutben; /* 0x224 */
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uint32 PAD[6];
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uint32 oobsyncc; /* 0x240 */
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uint32 oobseloutcen; /* 0x244 */
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uint32 PAD[6];
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uint32 oobsyncd; /* 0x260 */
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uint32 oobseloutden; /* 0x264 */
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uint32 PAD[38];
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uint32 oobaextwidth; /* 0x300 */
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uint32 oobainwidth; /* 0x304 */
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uint32 oobaoutwidth; /* 0x308 */
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uint32 PAD[5];
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uint32 oobbextwidth; /* 0x320 */
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uint32 oobbinwidth; /* 0x324 */
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uint32 oobboutwidth; /* 0x328 */
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uint32 PAD[5];
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uint32 oobcextwidth; /* 0x340 */
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uint32 oobcinwidth; /* 0x344 */
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uint32 oobcoutwidth; /* 0x348 */
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uint32 PAD[5];
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uint32 oobdextwidth; /* 0x360 */
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uint32 oobdinwidth; /* 0x364 */
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uint32 oobdoutwidth; /* 0x368 */
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uint32 PAD[37];
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uint32 ioctrlset; /* 0x400 */
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uint32 ioctrlclear; /* 0x404 */
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uint32 ioctrl; /* 0x408 */
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uint32 PAD[61];
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uint32 iostatus; /* 0x500 */
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uint32 PAD[127];
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uint32 ioctrlwidth; /* 0x700 */
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uint32 iostatuswidth; /* 0x704 */
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uint32 PAD[62];
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uint32 resetctrl; /* 0x800 */
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uint32 resetstatus; /* 0x804 */
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uint32 resetreadid; /* 0x808 */
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uint32 resetwriteid; /* 0x80c */
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uint32 PAD[60];
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uint32 errlogctrl; /* 0x900 */
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uint32 errlogdone; /* 0x904 */
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uint32 errlogstatus; /* 0x908 */
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uint32 errlogaddrlo; /* 0x90c */
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uint32 errlogaddrhi; /* 0x910 */
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uint32 errlogid; /* 0x914 */
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uint32 errloguser; /* 0x918 */
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uint32 errlogflags; /* 0x91c */
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uint32 PAD[56];
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uint32 intstatus; /* 0xa00 */
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uint32 PAD[255];
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uint32 config; /* 0xe00 */
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uint32 PAD[63];
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uint32 itcr; /* 0xf00 */
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uint32 PAD[3];
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uint32 itipooba; /* 0xf10 */
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uint32 itipoobb; /* 0xf14 */
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uint32 itipoobc; /* 0xf18 */
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uint32 itipoobd; /* 0xf1c */
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uint32 PAD[4];
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uint32 itipoobaout; /* 0xf30 */
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uint32 itipoobbout; /* 0xf34 */
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uint32 itipoobcout; /* 0xf38 */
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uint32 itipoobdout; /* 0xf3c */
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uint32 PAD[4];
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uint32 itopooba; /* 0xf50 */
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uint32 itopoobb; /* 0xf54 */
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uint32 itopoobc; /* 0xf58 */
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uint32 itopoobd; /* 0xf5c */
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uint32 PAD[4];
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uint32 itopoobain; /* 0xf70 */
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uint32 itopoobbin; /* 0xf74 */
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uint32 itopoobcin; /* 0xf78 */
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uint32 itopoobdin; /* 0xf7c */
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uint32 PAD[4];
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uint32 itopreset; /* 0xf90 */
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uint32 PAD[15];
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uint32 peripherialid4; /* 0xfd0 */
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uint32 peripherialid5; /* 0xfd4 */
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uint32 peripherialid6; /* 0xfd8 */
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uint32 peripherialid7; /* 0xfdc */
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uint32 peripherialid0; /* 0xfe0 */
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uint32 peripherialid1; /* 0xfe4 */
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uint32 peripherialid2; /* 0xfe8 */
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uint32 peripherialid3; /* 0xfec */
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uint32 componentid0; /* 0xff0 */
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uint32 componentid1; /* 0xff4 */
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uint32 componentid2; /* 0xff8 */
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uint32 componentid3; /* 0xffc */
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} aidmp_t;
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#endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
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/* Out-of-band Router registers */
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#define OOB_BUSCONFIG 0x020
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#define OOB_STATUSA 0x100
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#define OOB_STATUSB 0x104
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#define OOB_STATUSC 0x108
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#define OOB_STATUSD 0x10c
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#define OOB_ENABLEA0 0x200
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#define OOB_ENABLEA1 0x204
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#define OOB_ENABLEA2 0x208
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#define OOB_ENABLEA3 0x20c
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#define OOB_ENABLEB0 0x280
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#define OOB_ENABLEB1 0x284
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#define OOB_ENABLEB2 0x288
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#define OOB_ENABLEB3 0x28c
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#define OOB_ENABLEC0 0x300
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#define OOB_ENABLEC1 0x304
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#define OOB_ENABLEC2 0x308
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#define OOB_ENABLEC3 0x30c
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#define OOB_ENABLED0 0x380
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#define OOB_ENABLED1 0x384
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#define OOB_ENABLED2 0x388
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#define OOB_ENABLED3 0x38c
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#define OOB_ITCR 0xf00
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#define OOB_ITIPOOBA 0xf10
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#define OOB_ITIPOOBB 0xf14
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#define OOB_ITIPOOBC 0xf18
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#define OOB_ITIPOOBD 0xf1c
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#define OOB_ITOPOOBA 0xf30
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#define OOB_ITOPOOBB 0xf34
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#define OOB_ITOPOOBC 0xf38
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#define OOB_ITOPOOBD 0xf3c
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/* DMP wrapper registers */
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#define AI_OOBSELINA30 0x000
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#define AI_OOBSELINA74 0x004
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#define AI_OOBSELINB30 0x020
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#define AI_OOBSELINB74 0x024
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#define AI_OOBSELINC30 0x040
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#define AI_OOBSELINC74 0x044
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#define AI_OOBSELIND30 0x060
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#define AI_OOBSELIND74 0x064
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#define AI_OOBSELOUTA30 0x100
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#define AI_OOBSELOUTA74 0x104
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#define AI_OOBSELOUTB30 0x120
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#define AI_OOBSELOUTB74 0x124
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#define AI_OOBSELOUTC30 0x140
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#define AI_OOBSELOUTC74 0x144
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#define AI_OOBSELOUTD30 0x160
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#define AI_OOBSELOUTD74 0x164
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#define AI_OOBSYNCA 0x200
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#define AI_OOBSELOUTAEN 0x204
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#define AI_OOBSYNCB 0x220
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#define AI_OOBSELOUTBEN 0x224
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#define AI_OOBSYNCC 0x240
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#define AI_OOBSELOUTCEN 0x244
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#define AI_OOBSYNCD 0x260
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#define AI_OOBSELOUTDEN 0x264
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#define AI_OOBAEXTWIDTH 0x300
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#define AI_OOBAINWIDTH 0x304
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#define AI_OOBAOUTWIDTH 0x308
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#define AI_OOBBEXTWIDTH 0x320
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#define AI_OOBBINWIDTH 0x324
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#define AI_OOBBOUTWIDTH 0x328
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#define AI_OOBCEXTWIDTH 0x340
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#define AI_OOBCINWIDTH 0x344
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#define AI_OOBCOUTWIDTH 0x348
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#define AI_OOBDEXTWIDTH 0x360
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#define AI_OOBDINWIDTH 0x364
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#define AI_OOBDOUTWIDTH 0x368
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#define AI_IOCTRLSET 0x400
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#define AI_IOCTRLCLEAR 0x404
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#define AI_IOCTRL 0x408
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#define AI_IOSTATUS 0x500
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#define AI_RESETCTRL 0x800
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#define AI_RESETSTATUS 0x804
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#define AI_IOCTRLWIDTH 0x700
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#define AI_IOSTATUSWIDTH 0x704
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#define AI_RESETREADID 0x808
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#define AI_RESETWRITEID 0x80c
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#define AI_ERRLOGCTRL 0x900
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#define AI_ERRLOGDONE 0x904
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#define AI_ERRLOGSTATUS 0x908
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#define AI_ERRLOGADDRLO 0x90c
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#define AI_ERRLOGADDRHI 0x910
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#define AI_ERRLOGID 0x914
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#define AI_ERRLOGUSER 0x918
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#define AI_ERRLOGFLAGS 0x91c
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#define AI_INTSTATUS 0xa00
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#define AI_CONFIG 0xe00
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#define AI_ITCR 0xf00
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#define AI_ITIPOOBA 0xf10
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#define AI_ITIPOOBB 0xf14
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#define AI_ITIPOOBC 0xf18
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#define AI_ITIPOOBD 0xf1c
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#define AI_ITIPOOBAOUT 0xf30
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#define AI_ITIPOOBBOUT 0xf34
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#define AI_ITIPOOBCOUT 0xf38
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#define AI_ITIPOOBDOUT 0xf3c
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#define AI_ITOPOOBA 0xf50
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#define AI_ITOPOOBB 0xf54
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#define AI_ITOPOOBC 0xf58
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#define AI_ITOPOOBD 0xf5c
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#define AI_ITOPOOBAIN 0xf70
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#define AI_ITOPOOBBIN 0xf74
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#define AI_ITOPOOBCIN 0xf78
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#define AI_ITOPOOBDIN 0xf7c
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#define AI_ITOPRESET 0xf90
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#define AI_PERIPHERIALID4 0xfd0
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#define AI_PERIPHERIALID5 0xfd4
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#define AI_PERIPHERIALID6 0xfd8
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#define AI_PERIPHERIALID7 0xfdc
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#define AI_PERIPHERIALID0 0xfe0
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#define AI_PERIPHERIALID1 0xfe4
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#define AI_PERIPHERIALID2 0xfe8
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#define AI_PERIPHERIALID3 0xfec
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#define AI_COMPONENTID0 0xff0
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#define AI_COMPONENTID1 0xff4
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#define AI_COMPONENTID2 0xff8
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#define AI_COMPONENTID3 0xffc
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||
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||
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/* resetctrl */
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||
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#define AIRC_RESET 1
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||
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||
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/* errlogctrl */
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||
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#define AIELC_TO_EXP_MASK 0x0000001f0 /* backplane timeout exponent */
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||
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#define AIELC_TO_EXP_SHIFT 4
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||
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#define AIELC_TO_ENAB_SHIFT 9 /* backplane timeout enable */
|
||
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|
|
||
|
|
/* errlogdone */
|
||
|
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#define AIELD_ERRDONE_MASK 0x3
|
||
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|
|
||
|
|
/* errlogstatus */
|
||
|
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#define AIELS_TIMEOUT_MASK 0x3
|
||
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|
|
||
|
|
/* config */
|
||
|
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#define AICFG_OOB 0x00000020
|
||
|
|
#define AICFG_IOS 0x00000010
|
||
|
|
#define AICFG_IOC 0x00000008
|
||
|
|
#define AICFG_TO 0x00000004
|
||
|
|
#define AICFG_ERRL 0x00000002
|
||
|
|
#define AICFG_RST 0x00000001
|
||
|
|
|
||
|
|
/* bit defines for AI_OOBSELOUTB74 reg */
|
||
|
|
#define OOB_SEL_OUTEN_B_5 15
|
||
|
|
#define OOB_SEL_OUTEN_B_6 23
|
||
|
|
|
||
|
|
/* AI_OOBSEL for A/B/C/D, 0-7 */
|
||
|
|
#define AI_OOBSEL_MASK 0x1F
|
||
|
|
#define AI_OOBSEL_0_SHIFT 0
|
||
|
|
#define AI_OOBSEL_1_SHIFT 8
|
||
|
|
#define AI_OOBSEL_2_SHIFT 16
|
||
|
|
#define AI_OOBSEL_3_SHIFT 24
|
||
|
|
#define AI_OOBSEL_4_SHIFT 0
|
||
|
|
#define AI_OOBSEL_5_SHIFT 8
|
||
|
|
#define AI_OOBSEL_6_SHIFT 16
|
||
|
|
#define AI_OOBSEL_7_SHIFT 24
|
||
|
|
#define AI_IOCTRL_ENABLE_D11_PME (1 << 14)
|
||
|
|
|
||
|
|
#endif /* _AIDMP_H */
|