866 lines
23 KiB
C
866 lines
23 KiB
C
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/*
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* MSGBUF network driver ioctl/indication encoding
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* Broadcom 802.11abg Networking Device Driver
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*
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* Definitions subject to change without notice.
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*
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* Portions of this code are copyright (c) 2017 Cypress Semiconductor Corporation
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: bcmmsgbuf.h 541060 2015-03-13 23:28:01Z $
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*/
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#ifndef _bcmmsgbuf_h_
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#define _bcmmsgbuf_h_
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#include <proto/ethernet.h>
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#include <wlioctl.h>
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#include <bcmpcie.h>
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#define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN
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#define D2H_EPOCH_MODULO 253 /* sequence number wrap */
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#define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1)
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#define H2D_EPOCH_MODULO 253 /* sequence number wrap */
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#define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1)
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#define H2DRING_TXPOST_ITEMSIZE 48
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#define H2DRING_RXPOST_ITEMSIZE 32
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#define H2DRING_CTRL_SUB_ITEMSIZE 40
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#define D2HRING_TXCMPLT_ITEMSIZE 16
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#define D2HRING_RXCMPLT_ITEMSIZE 32
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#define D2HRING_CTRL_CMPLT_ITEMSIZE 24
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#define H2DRING_TXPOST_MAX_ITEM 512
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#define H2DRING_RXPOST_MAX_ITEM 512
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#define H2DRING_CTRL_SUB_MAX_ITEM 64
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#define D2HRING_TXCMPLT_MAX_ITEM 1024
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#define D2HRING_RXCMPLT_MAX_ITEM 512
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#define D2HRING_CTRL_CMPLT_MAX_ITEM 64
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enum {
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DNGL_TO_HOST_MSGBUF,
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HOST_TO_DNGL_MSGBUF
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};
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enum {
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HOST_TO_DNGL_TXP_DATA,
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HOST_TO_DNGL_RXP_DATA,
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HOST_TO_DNGL_CTRL,
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DNGL_TO_HOST_DATA,
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DNGL_TO_HOST_CTRL
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};
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#define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE
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#ifdef PCIE_API_REV1
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#define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0)
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#define BCMMSGBUF_API_IFIDX(a) 0
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#define BCMMSGBUF_API_SEQNUM(a) 0
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#define BCMMSGBUF_IOCTL_XTID(a) 0
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#define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id)
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#define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b)
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#define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b)
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#define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b))
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#define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b)
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#else /* PCIE_API_REV1 */
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#define BCMMSGBUF_API_IFIDX(a) ((a)->if_id)
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#define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id)
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#define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no)
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#define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id)
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#define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b))
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#define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b))
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#define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b))
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#define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b))
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#endif /* PCIE_API_REV1 */
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/* utility data structures */
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union addr64 {
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struct {
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uint32 low;
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uint32 high;
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};
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struct {
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uint32 low_addr;
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uint32 high_addr;
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};
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uint64 u64;
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} DECLSPEC_ALIGN(8);
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typedef union addr64 bcm_addr64_t;
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/* IOCTL req Hdr */
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/* cmn Msg Hdr */
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typedef struct cmn_msg_hdr {
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/** message type */
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uint8 msg_type;
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/** interface index this is valid for */
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uint8 if_id;
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/* flags */
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uint8 flags;
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/** sequence number */
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uint8 epoch;
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/** packet Identifier for the associated host buffer */
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uint32 request_id;
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} cmn_msg_hdr_t;
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/** message type */
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typedef enum bcmpcie_msgtype {
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MSG_TYPE_GEN_STATUS = 0x1,
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MSG_TYPE_RING_STATUS = 0x2,
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MSG_TYPE_FLOW_RING_CREATE = 0x3,
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MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4,
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MSG_TYPE_FLOW_RING_DELETE = 0x5,
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MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6,
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MSG_TYPE_FLOW_RING_FLUSH = 0x7,
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MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8,
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MSG_TYPE_IOCTLPTR_REQ = 0x9,
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MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA,
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MSG_TYPE_IOCTLRESP_BUF_POST = 0xB,
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MSG_TYPE_IOCTL_CMPLT = 0xC,
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MSG_TYPE_EVENT_BUF_POST = 0xD,
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MSG_TYPE_WL_EVENT = 0xE,
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MSG_TYPE_TX_POST = 0xF,
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MSG_TYPE_TX_STATUS = 0x10,
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MSG_TYPE_RXBUF_POST = 0x11,
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MSG_TYPE_RX_CMPLT = 0x12,
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MSG_TYPE_LPBK_DMAXFER = 0x13,
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MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14,
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MSG_TYPE_FLOW_RING_RESUME = 0x15,
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MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16,
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MSG_TYPE_FLOW_RING_SUSPEND = 0x17,
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MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18,
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MSG_TYPE_INFO_BUF_POST = 0x19,
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MSG_TYPE_INFO_BUF_CMPLT = 0x1A,
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MSG_TYPE_H2D_RING_CREATE = 0x1B,
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MSG_TYPE_D2H_RING_CREATE = 0x1C,
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MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D,
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MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E,
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MSG_TYPE_H2D_RING_CONFIG = 0x1F,
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MSG_TYPE_D2H_RING_CONFIG = 0x20,
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MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21,
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MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22,
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MSG_TYPE_H2D_MAILBOX_DATA = 0x23,
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MSG_TYPE_D2H_MAILBOX_DATA = 0x24,
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MSG_TYPE_API_MAX_RSVD = 0x3F
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} bcmpcie_msg_type_t;
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typedef enum bcmpcie_msgtype_int {
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MSG_TYPE_INTERNAL_USE_START = 0x40,
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MSG_TYPE_EVENT_PYLD = 0x41,
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MSG_TYPE_IOCT_PYLD = 0x42,
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MSG_TYPE_RX_PYLD = 0x43,
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MSG_TYPE_HOST_FETCH = 0x44,
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MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45,
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MSG_TYPE_TXMETADATA_PYLD = 0x46,
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MSG_TYPE_INDX_UPDATE = 0x47
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} bcmpcie_msgtype_int_t;
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typedef enum bcmpcie_msgtype_u {
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MSG_TYPE_TX_BATCH_POST = 0x80,
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MSG_TYPE_IOCTL_REQ = 0x81,
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MSG_TYPE_HOST_EVNT = 0x82, /* console related */
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MSG_TYPE_LOOPBACK = 0x83
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} bcmpcie_msgtype_u_t;
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/**
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* D2H ring host wakeup soft doorbell, override the PCIE doorbell.
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* Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE
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* Transl0 to write specified value to host address.
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*
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* Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register
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* and value is Core/Thread context. Host will ensure routing the 32bit address
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* offerred to PCIE to the mapped register.
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*
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* D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL
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*/
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typedef struct bcmpcie_soft_doorbell {
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uint32 value; /* host defined value to be written, eg HW threadid */
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bcm_addr64_t haddr; /* host address, eg thread wakeup register address */
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uint16 items; /* interrupt coalescing: item count before wakeup */
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uint16 msecs; /* interrupt coalescing: timeout in millisecs */
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} bcmpcie_soft_doorbell_t;
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/* if_id */
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#define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5
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#define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7
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#define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \
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(BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
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#define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0
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#define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F
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#define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \
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(BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
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/* flags */
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#define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1
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#define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2
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#define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80
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/* IOCTL request message */
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typedef struct ioctl_req_msg {
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/** common message header */
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cmn_msg_hdr_t cmn_hdr;
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/** ioctl command type */
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uint32 cmd;
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/** ioctl transaction ID, to pair with a ioctl response */
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uint16 trans_id;
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/** input arguments buffer len */
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uint16 input_buf_len;
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/** expected output len */
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uint16 output_buf_len;
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/** to align the host address on 8 byte boundary */
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uint16 rsvd[3];
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/** always align on 8 byte boundary */
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bcm_addr64_t host_input_buf_addr;
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/* rsvd */
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uint32 rsvd1[2];
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} ioctl_req_msg_t;
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/** buffer post messages for device to use to return IOCTL responses, Events */
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typedef struct ioctl_resp_evt_buf_post_msg {
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/** common message header */
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cmn_msg_hdr_t cmn_hdr;
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/** length of the host buffer supplied */
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uint16 host_buf_len;
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/** to align the host address on 8 byte boundary */
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uint16 reserved[3];
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/** always align on 8 byte boundary */
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bcm_addr64_t host_buf_addr;
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uint32 rsvd[4];
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} ioctl_resp_evt_buf_post_msg_t;
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typedef struct pcie_dma_xfer_params {
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/** common message header */
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cmn_msg_hdr_t cmn_hdr;
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/** always align on 8 byte boundary */
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bcm_addr64_t host_input_buf_addr;
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/** always align on 8 byte boundary */
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bcm_addr64_t host_ouput_buf_addr;
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/** length of transfer */
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uint32 xfer_len;
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/** delay before doing the src txfer */
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uint32 srcdelay;
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/** delay before doing the dest txfer */
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uint32 destdelay;
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uint32 rsvd;
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} pcie_dma_xfer_params_t;
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/** Complete msgbuf hdr for flow ring update from host to dongle */
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typedef struct tx_flowring_create_request {
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cmn_msg_hdr_t msg;
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uint8 da[ETHER_ADDR_LEN];
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uint8 sa[ETHER_ADDR_LEN];
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uint8 tid;
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uint8 if_flags;
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uint16 flow_ring_id;
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uint8 tc;
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uint8 priority;
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uint16 int_vector;
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uint16 max_items;
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uint16 len_item;
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bcm_addr64_t flow_ring_ptr;
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} tx_flowring_create_request_t;
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typedef struct tx_flowring_delete_request {
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cmn_msg_hdr_t msg;
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uint16 flow_ring_id;
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uint16 reason;
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uint32 rsvd[7];
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} tx_flowring_delete_request_t;
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typedef struct tx_flowring_flush_request {
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cmn_msg_hdr_t msg;
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uint16 flow_ring_id;
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uint16 reason;
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uint32 rsvd[7];
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} tx_flowring_flush_request_t;
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/** Subtypes for ring_config_req control message */
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typedef enum ring_config_subtype {
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/** Default D2H PCIE doorbell override using ring_config_req msg */
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D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */
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D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */
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} ring_config_subtype_t;
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typedef struct ring_config_req {
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cmn_msg_hdr_t msg;
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uint16 subtype;
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uint16 ring_id;
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uint32 rsvd;
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union {
|
||
|
|
uint32 data[6];
|
||
|
|
/** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */
|
||
|
|
bcmpcie_soft_doorbell_t soft_doorbell;
|
||
|
|
};
|
||
|
|
} ring_config_req_t;
|
||
|
|
|
||
|
|
typedef union ctrl_submit_item {
|
||
|
|
ioctl_req_msg_t ioctl_req;
|
||
|
|
ioctl_resp_evt_buf_post_msg_t resp_buf_post;
|
||
|
|
pcie_dma_xfer_params_t dma_xfer;
|
||
|
|
tx_flowring_create_request_t flow_create;
|
||
|
|
tx_flowring_delete_request_t flow_delete;
|
||
|
|
tx_flowring_flush_request_t flow_flush;
|
||
|
|
ring_config_req_t ring_config_req;
|
||
|
|
unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE];
|
||
|
|
} ctrl_submit_item_t;
|
||
|
|
|
||
|
|
/** Control Completion messages (20 bytes) */
|
||
|
|
typedef struct compl_msg_hdr {
|
||
|
|
/** status for the completion */
|
||
|
|
int16 status;
|
||
|
|
/** submisison flow ring id which generated this status */
|
||
|
|
uint16 flow_ring_id;
|
||
|
|
} compl_msg_hdr_t;
|
||
|
|
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
typedef uint32 dma_done_t;
|
||
|
|
|
||
|
|
/* completion header status codes */
|
||
|
|
#define BCMPCIE_SUCCESS 0
|
||
|
|
#define BCMPCIE_NOTFOUND 1
|
||
|
|
#define BCMPCIE_NOMEM 2
|
||
|
|
#define BCMPCIE_BADOPTION 3
|
||
|
|
#define BCMPCIE_RING_IN_USE 4
|
||
|
|
#define BCMPCIE_RING_ID_INVALID 5
|
||
|
|
#define BCMPCIE_PKT_FLUSH 6
|
||
|
|
#define BCMPCIE_NO_EVENT_BUF 7
|
||
|
|
#define BCMPCIE_NO_RX_BUF 8
|
||
|
|
#define BCMPCIE_NO_IOCTLRESP_BUF 9
|
||
|
|
#define BCMPCIE_MAX_IOCTLRESP_BUF 10
|
||
|
|
#define BCMPCIE_MAX_EVENT_BUF 11
|
||
|
|
|
||
|
|
/** IOCTL completion response */
|
||
|
|
typedef struct ioctl_compl_resp_msg {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
/** response buffer len where a host buffer is involved */
|
||
|
|
uint16 resp_len;
|
||
|
|
/** transaction id to pair with a request */
|
||
|
|
uint16 trans_id;
|
||
|
|
/** cmd id */
|
||
|
|
uint32 cmd;
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} ioctl_comp_resp_msg_t;
|
||
|
|
|
||
|
|
/** IOCTL request acknowledgement */
|
||
|
|
typedef struct ioctl_req_ack_msg {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
/** cmd id */
|
||
|
|
uint32 cmd;
|
||
|
|
uint32 rsvd;
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} ioctl_req_ack_msg_t;
|
||
|
|
|
||
|
|
/** WL event message: send from device to host */
|
||
|
|
typedef struct wlevent_req_msg {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
/** event data len valid with the event buffer */
|
||
|
|
uint16 event_data_len;
|
||
|
|
/** sequence number */
|
||
|
|
uint16 seqnum;
|
||
|
|
/** rsvd */
|
||
|
|
uint32 rsvd;
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} wlevent_req_msg_t;
|
||
|
|
|
||
|
|
/** dma xfer complete message */
|
||
|
|
typedef struct pcie_dmaxfer_cmplt {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} pcie_dmaxfer_cmplt_t;
|
||
|
|
|
||
|
|
/** general status message */
|
||
|
|
typedef struct pcie_gen_status {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} pcie_gen_status_t;
|
||
|
|
|
||
|
|
/** ring status message */
|
||
|
|
typedef struct pcie_ring_status {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
/** message which firmware couldn't decode */
|
||
|
|
uint16 write_idx;
|
||
|
|
uint16 rsvd[3];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} pcie_ring_status_t;
|
||
|
|
|
||
|
|
typedef struct tx_flowring_create_response {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
compl_msg_hdr_t cmplt;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} tx_flowring_create_response_t;
|
||
|
|
|
||
|
|
typedef struct tx_flowring_delete_response {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
compl_msg_hdr_t cmplt;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} tx_flowring_delete_response_t;
|
||
|
|
|
||
|
|
typedef struct tx_flowring_flush_response {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
compl_msg_hdr_t cmplt;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} tx_flowring_flush_response_t;
|
||
|
|
|
||
|
|
/** Common layout of all d2h control messages */
|
||
|
|
typedef struct ctrl_compl_msg {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} ctrl_compl_msg_t;
|
||
|
|
|
||
|
|
typedef struct ring_config_resp {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} ring_config_resp_t;
|
||
|
|
|
||
|
|
typedef union ctrl_completion_item {
|
||
|
|
ioctl_comp_resp_msg_t ioctl_resp;
|
||
|
|
wlevent_req_msg_t event;
|
||
|
|
ioctl_req_ack_msg_t ioct_ack;
|
||
|
|
pcie_dmaxfer_cmplt_t pcie_xfer_cmplt;
|
||
|
|
pcie_gen_status_t pcie_gen_status;
|
||
|
|
pcie_ring_status_t pcie_ring_status;
|
||
|
|
tx_flowring_create_response_t txfl_create_resp;
|
||
|
|
tx_flowring_delete_response_t txfl_delete_resp;
|
||
|
|
tx_flowring_flush_response_t txfl_flush_resp;
|
||
|
|
ctrl_compl_msg_t ctrl_compl;
|
||
|
|
ring_config_resp_t ring_config_resp;
|
||
|
|
unsigned char check[D2HRING_CTRL_CMPLT_ITEMSIZE];
|
||
|
|
} ctrl_completion_item_t;
|
||
|
|
|
||
|
|
/** H2D Rxpost ring work items */
|
||
|
|
typedef struct host_rxbuf_post {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** provided meta data buffer len */
|
||
|
|
uint16 metadata_buf_len;
|
||
|
|
/** provided data buffer len to receive data */
|
||
|
|
uint16 data_buf_len;
|
||
|
|
/** alignment to make the host buffers start on 8 byte boundary */
|
||
|
|
uint32 rsvd;
|
||
|
|
/** provided meta data buffer */
|
||
|
|
bcm_addr64_t metadata_buf_addr;
|
||
|
|
/** provided data buffer to receive data */
|
||
|
|
bcm_addr64_t data_buf_addr;
|
||
|
|
} host_rxbuf_post_t;
|
||
|
|
|
||
|
|
typedef union rxbuf_submit_item {
|
||
|
|
host_rxbuf_post_t rxpost;
|
||
|
|
unsigned char check[H2DRING_RXPOST_ITEMSIZE];
|
||
|
|
} rxbuf_submit_item_t;
|
||
|
|
|
||
|
|
|
||
|
|
/** D2H Rxcompletion ring work items */
|
||
|
|
typedef struct host_rxbuf_cmpl {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
/** filled up meta data len */
|
||
|
|
uint16 metadata_len;
|
||
|
|
/** filled up buffer len to receive data */
|
||
|
|
uint16 data_len;
|
||
|
|
/** offset in the host rx buffer where the data starts */
|
||
|
|
uint16 data_offset;
|
||
|
|
/** offset in the host rx buffer where the data starts */
|
||
|
|
uint16 flags;
|
||
|
|
/** rx status */
|
||
|
|
uint32 rx_status_0;
|
||
|
|
uint32 rx_status_1;
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} host_rxbuf_cmpl_t;
|
||
|
|
|
||
|
|
typedef union rxbuf_complete_item {
|
||
|
|
host_rxbuf_cmpl_t rxcmpl;
|
||
|
|
unsigned char check[D2HRING_RXCMPLT_ITEMSIZE];
|
||
|
|
} rxbuf_complete_item_t;
|
||
|
|
|
||
|
|
|
||
|
|
typedef struct host_txbuf_post {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** eth header */
|
||
|
|
uint8 txhdr[ETHER_HDR_LEN];
|
||
|
|
/** flags */
|
||
|
|
uint8 flags;
|
||
|
|
/** number of segments */
|
||
|
|
uint8 seg_cnt;
|
||
|
|
|
||
|
|
/** provided meta data buffer for txstatus */
|
||
|
|
bcm_addr64_t metadata_buf_addr;
|
||
|
|
/** provided data buffer to receive data */
|
||
|
|
bcm_addr64_t data_buf_addr;
|
||
|
|
/** provided meta data buffer len */
|
||
|
|
uint16 metadata_buf_len;
|
||
|
|
/** provided data buffer len to receive data */
|
||
|
|
uint16 data_len;
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
} host_txbuf_post_t;
|
||
|
|
|
||
|
|
#define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01
|
||
|
|
#define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02
|
||
|
|
|
||
|
|
#define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */
|
||
|
|
#define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */
|
||
|
|
|
||
|
|
|
||
|
|
#define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5
|
||
|
|
#define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT)
|
||
|
|
|
||
|
|
/* These are added to fix up compile issues */
|
||
|
|
#define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3
|
||
|
|
#define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11
|
||
|
|
#define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT
|
||
|
|
#define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK
|
||
|
|
|
||
|
|
/** H2D Txpost ring work items */
|
||
|
|
typedef union txbuf_submit_item {
|
||
|
|
host_txbuf_post_t txpost;
|
||
|
|
unsigned char check[H2DRING_TXPOST_ITEMSIZE];
|
||
|
|
} txbuf_submit_item_t;
|
||
|
|
|
||
|
|
/** D2H Txcompletion ring work items */
|
||
|
|
typedef struct host_txbuf_cmpl {
|
||
|
|
/** common message header */
|
||
|
|
cmn_msg_hdr_t cmn_hdr;
|
||
|
|
/** completion message header */
|
||
|
|
compl_msg_hdr_t compl_hdr;
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
/** provided meta data len */
|
||
|
|
uint16 metadata_len;
|
||
|
|
/** WLAN side txstatus */
|
||
|
|
uint16 tx_status;
|
||
|
|
};
|
||
|
|
/** XOR checksum or a magic number to audit DMA done */
|
||
|
|
dma_done_t marker;
|
||
|
|
};
|
||
|
|
} host_txbuf_cmpl_t;
|
||
|
|
|
||
|
|
typedef union txbuf_complete_item {
|
||
|
|
host_txbuf_cmpl_t txcmpl;
|
||
|
|
unsigned char check[D2HRING_TXCMPLT_ITEMSIZE];
|
||
|
|
} txbuf_complete_item_t;
|
||
|
|
|
||
|
|
#define BCMPCIE_D2H_METADATA_HDRLEN 4
|
||
|
|
#define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4)
|
||
|
|
|
||
|
|
/** ret buf struct */
|
||
|
|
typedef struct ret_buf_ptr {
|
||
|
|
uint32 low_addr;
|
||
|
|
uint32 high_addr;
|
||
|
|
} ret_buf_t;
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef PCIE_API_REV1
|
||
|
|
|
||
|
|
/* ioctl specific hdr */
|
||
|
|
typedef struct ioctl_hdr {
|
||
|
|
uint16 cmd;
|
||
|
|
uint16 retbuf_len;
|
||
|
|
uint32 cmd_id;
|
||
|
|
} ioctl_hdr_t;
|
||
|
|
|
||
|
|
typedef struct ioctlptr_hdr {
|
||
|
|
uint16 cmd;
|
||
|
|
uint16 retbuf_len;
|
||
|
|
uint16 buflen;
|
||
|
|
uint16 rsvd;
|
||
|
|
uint32 cmd_id;
|
||
|
|
} ioctlptr_hdr_t;
|
||
|
|
|
||
|
|
#else /* PCIE_API_REV1 */
|
||
|
|
|
||
|
|
typedef struct ioctl_req_hdr {
|
||
|
|
uint32 pkt_id; /**< Packet ID */
|
||
|
|
uint32 cmd; /**< IOCTL ID */
|
||
|
|
uint16 retbuf_len;
|
||
|
|
uint16 buflen;
|
||
|
|
uint16 xt_id; /**< transaction ID */
|
||
|
|
uint16 rsvd[1];
|
||
|
|
} ioctl_req_hdr_t;
|
||
|
|
|
||
|
|
#endif /* PCIE_API_REV1 */
|
||
|
|
|
||
|
|
|
||
|
|
/** Complete msgbuf hdr for ioctl from host to dongle */
|
||
|
|
typedef struct ioct_reqst_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
#ifdef PCIE_API_REV1
|
||
|
|
ioctl_hdr_t ioct_hdr;
|
||
|
|
#else
|
||
|
|
ioctl_req_hdr_t ioct_hdr;
|
||
|
|
#endif
|
||
|
|
ret_buf_t ret_buf;
|
||
|
|
} ioct_reqst_hdr_t;
|
||
|
|
|
||
|
|
typedef struct ioctptr_reqst_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
#ifdef PCIE_API_REV1
|
||
|
|
ioctlptr_hdr_t ioct_hdr;
|
||
|
|
#else
|
||
|
|
ioctl_req_hdr_t ioct_hdr;
|
||
|
|
#endif
|
||
|
|
ret_buf_t ret_buf;
|
||
|
|
ret_buf_t ioct_buf;
|
||
|
|
} ioctptr_reqst_hdr_t;
|
||
|
|
|
||
|
|
/** ioctl response header */
|
||
|
|
typedef struct ioct_resp_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
#ifdef PCIE_API_REV1
|
||
|
|
uint32 cmd_id;
|
||
|
|
#else
|
||
|
|
uint32 pkt_id;
|
||
|
|
#endif
|
||
|
|
uint32 status;
|
||
|
|
uint32 ret_len;
|
||
|
|
uint32 inline_data;
|
||
|
|
#ifdef PCIE_API_REV1
|
||
|
|
#else
|
||
|
|
uint16 xt_id; /**< transaction ID */
|
||
|
|
uint16 rsvd[1];
|
||
|
|
#endif
|
||
|
|
} ioct_resp_hdr_t;
|
||
|
|
|
||
|
|
/* ioct resp header used in dongle */
|
||
|
|
/* ret buf hdr will be stripped off inside dongle itself */
|
||
|
|
typedef struct msgbuf_ioctl_resp {
|
||
|
|
ioct_resp_hdr_t ioct_hdr;
|
||
|
|
ret_buf_t ret_buf; /**< ret buf pointers */
|
||
|
|
} msgbuf_ioct_resp_t;
|
||
|
|
|
||
|
|
/** WL event hdr info */
|
||
|
|
typedef struct wl_event_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint16 event;
|
||
|
|
uint8 flags;
|
||
|
|
uint8 rsvd;
|
||
|
|
uint16 retbuf_len;
|
||
|
|
uint16 rsvd1;
|
||
|
|
uint32 rxbufid;
|
||
|
|
} wl_event_hdr_t;
|
||
|
|
|
||
|
|
#define TXDESCR_FLOWID_PCIELPBK_1 0xFF
|
||
|
|
#define TXDESCR_FLOWID_PCIELPBK_2 0xFE
|
||
|
|
|
||
|
|
typedef struct txbatch_lenptr_tup {
|
||
|
|
uint32 pktid;
|
||
|
|
uint16 pktlen;
|
||
|
|
uint16 rsvd;
|
||
|
|
ret_buf_t ret_buf; /**< ret buf pointers */
|
||
|
|
} txbatch_lenptr_tup_t;
|
||
|
|
|
||
|
|
typedef struct txbatch_cmn_msghdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint8 priority;
|
||
|
|
uint8 hdrlen;
|
||
|
|
uint8 pktcnt;
|
||
|
|
uint8 flowid;
|
||
|
|
uint8 txhdr[ETHER_HDR_LEN];
|
||
|
|
uint16 rsvd;
|
||
|
|
} txbatch_cmn_msghdr_t;
|
||
|
|
|
||
|
|
typedef struct txbatch_msghdr {
|
||
|
|
txbatch_cmn_msghdr_t txcmn;
|
||
|
|
txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */
|
||
|
|
} txbatch_msghdr_t;
|
||
|
|
|
||
|
|
/* TX desc posting header */
|
||
|
|
typedef struct tx_lenptr_tup {
|
||
|
|
uint16 pktlen;
|
||
|
|
uint16 rsvd;
|
||
|
|
ret_buf_t ret_buf; /**< ret buf pointers */
|
||
|
|
} tx_lenptr_tup_t;
|
||
|
|
|
||
|
|
typedef struct txdescr_cmn_msghdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint8 priority;
|
||
|
|
uint8 hdrlen;
|
||
|
|
uint8 descrcnt;
|
||
|
|
uint8 flowid;
|
||
|
|
uint32 pktid;
|
||
|
|
} txdescr_cmn_msghdr_t;
|
||
|
|
|
||
|
|
typedef struct txdescr_msghdr {
|
||
|
|
txdescr_cmn_msghdr_t txcmn;
|
||
|
|
uint8 txhdr[ETHER_HDR_LEN];
|
||
|
|
uint16 rsvd;
|
||
|
|
tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */
|
||
|
|
} txdescr_msghdr_t;
|
||
|
|
|
||
|
|
/** Tx status header info */
|
||
|
|
typedef struct txstatus_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint32 pktid;
|
||
|
|
} txstatus_hdr_t;
|
||
|
|
|
||
|
|
/** RX bufid-len-ptr tuple */
|
||
|
|
typedef struct rx_lenptr_tup {
|
||
|
|
uint32 rxbufid;
|
||
|
|
uint16 len;
|
||
|
|
uint16 rsvd2;
|
||
|
|
ret_buf_t ret_buf; /**< ret buf pointers */
|
||
|
|
} rx_lenptr_tup_t;
|
||
|
|
|
||
|
|
/** Rx descr Post hdr info */
|
||
|
|
typedef struct rxdesc_msghdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint16 rsvd0;
|
||
|
|
uint8 rsvd1;
|
||
|
|
uint8 descnt;
|
||
|
|
rx_lenptr_tup_t rx_tup[0];
|
||
|
|
} rxdesc_msghdr_t;
|
||
|
|
|
||
|
|
/** RX complete tuples */
|
||
|
|
typedef struct rxcmplt_tup {
|
||
|
|
uint16 retbuf_len;
|
||
|
|
uint16 data_offset;
|
||
|
|
uint32 rxstatus0;
|
||
|
|
uint32 rxstatus1;
|
||
|
|
uint32 rxbufid;
|
||
|
|
} rxcmplt_tup_t;
|
||
|
|
|
||
|
|
/** RX complete messge hdr */
|
||
|
|
typedef struct rxcmplt_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint16 rsvd0;
|
||
|
|
uint16 rxcmpltcnt;
|
||
|
|
rxcmplt_tup_t rx_tup[0];
|
||
|
|
} rxcmplt_hdr_t;
|
||
|
|
|
||
|
|
typedef struct hostevent_hdr {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint32 evnt_pyld;
|
||
|
|
} hostevent_hdr_t;
|
||
|
|
|
||
|
|
typedef struct dma_xfer_params {
|
||
|
|
uint32 src_physaddr_hi;
|
||
|
|
uint32 src_physaddr_lo;
|
||
|
|
uint32 dest_physaddr_hi;
|
||
|
|
uint32 dest_physaddr_lo;
|
||
|
|
uint32 len;
|
||
|
|
uint32 srcdelay;
|
||
|
|
uint32 destdelay;
|
||
|
|
} dma_xfer_params_t;
|
||
|
|
|
||
|
|
enum {
|
||
|
|
HOST_EVENT_CONS_CMD = 1
|
||
|
|
};
|
||
|
|
|
||
|
|
/* defines for flags */
|
||
|
|
#define MSGBUF_IOC_ACTION_MASK 0x1
|
||
|
|
|
||
|
|
#define MAX_SUSPEND_REQ 15
|
||
|
|
|
||
|
|
typedef struct tx_idle_flowring_suspend_request {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint16 ring_id[MAX_SUSPEND_REQ]; /**< ring Id's */
|
||
|
|
uint16 num; /**< number of flowid's to suspend */
|
||
|
|
} tx_idle_flowring_suspend_request_t;
|
||
|
|
|
||
|
|
typedef struct tx_idle_flowring_suspend_response {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
compl_msg_hdr_t cmplt;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
dma_done_t marker;
|
||
|
|
} tx_idle_flowring_suspend_response_t;
|
||
|
|
|
||
|
|
typedef struct tx_idle_flowring_resume_request {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
uint16 flow_ring_id;
|
||
|
|
uint16 reason;
|
||
|
|
uint32 rsvd[7];
|
||
|
|
} tx_idle_flowring_resume_request_t;
|
||
|
|
|
||
|
|
typedef struct tx_idle_flowring_resume_response {
|
||
|
|
cmn_msg_hdr_t msg;
|
||
|
|
compl_msg_hdr_t cmplt;
|
||
|
|
uint32 rsvd[2];
|
||
|
|
dma_done_t marker;
|
||
|
|
} tx_idle_flowring_resume_response_t;
|
||
|
|
|
||
|
|
#endif /* _bcmmsgbuf_h_ */
|