408 lines
11 KiB
C
408 lines
11 KiB
C
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/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/of.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/of_platform.h>
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#include <soc/tegra/bpmp_abi.h>
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#include <soc/tegra/tegra_bpmp.h>
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#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
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#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
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#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
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#define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4
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#define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1)
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#define P2U_CONTROL_GEN1 0x78
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#define P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_LINK_STATUS BIT(2)
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#define P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_EIOS BIT(3)
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#define P2U_RX_DEBOUNCE_TIME 0xa4
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#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xFFFF
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#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
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#define P2U_RX_MARGIN_SW_INT_EN 0xe0
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#define P2U_RX_MARGIN_SW_INT_EN_READINESS BIT(0)
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#define P2U_RX_MARGIN_SW_INT_EN_MARGIN_START BIT(1)
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#define P2U_RX_MARGIN_SW_INT_EN_MARGIN_CHANGE BIT(2)
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#define P2U_RX_MARGIN_SW_INT_EN_MARGIN_STOP BIT(3)
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#define P2U_RX_MARGIN_SW_INT 0xe4
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#define P2U_RX_MARGIN_SW_INT_MASK 0xf
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#define P2U_RX_MARGIN_SW_INT_READINESS BIT(0)
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#define P2U_RX_MARGIN_SW_INT_MARGIN_START BIT(1)
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#define P2U_RX_MARGIN_SW_INT_MARGIN_CHANGE BIT(2)
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#define P2U_RX_MARGIN_SW_INT_MARGIN_STOP BIT(3)
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#define P2U_RX_MARGIN_SW_STATUS 0xe8
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#define P2U_RX_MARGIN_SW_STATUS_MARGIN_SW_READY BIT(0)
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#define P2U_RX_MARGIN_SW_STATUS_MARGIN_READY BIT(1)
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#define P2U_RX_MARGIN_SW_STATUS_PHY_MARGIN_STATUS BIT(2)
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#define P2U_RX_MARGIN_SW_STATUS_PHY_MARGIN_ERROR_STATUS BIT(3)
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#define P2U_RX_MARGIN_CTRL 0xec
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#define P2U_RX_MARGIN_CTRL_EN BIT(0)
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#define P2U_RX_MARGIN_CTRL_N_BLKS_MASK GENMASK(21, 14)
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#define P2U_RX_MARGIN_CTRL_N_BLKS_SHIFT 14
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/* Any value between {0x80, 0xFF}, randomly selected 0x81 */
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#define N_BLKS_COUNT 0x81
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#define P2U_RX_MARGIN_STATUS 0xf0
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#define P2U_RX_MARGIN_STATUS_ERRORS_MASK GENMASK(15, 0)
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#define P2U_RX_MARGIN_CONTROL 0xf0
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#define P2U_RX_MARGIN_CONTROL_START BIT(0)
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#define RX_MARGIN_START_CHANGE (1)
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#define RX_MARGIN_STOP (2)
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#define RX_MARGIN_GET_MARGIN (3)
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struct tegra_p2u {
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void __iomem *base;
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struct device *dev;
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u32 id;
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struct work_struct rx_margin_work;
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u32 next_state;
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spinlock_t next_state_lock; /* lock for next_state */
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bool enable_lm;
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bool disable_uphy_rx_idle;
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};
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struct margin_ctrl {
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u32 en:1;
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u32 clr:1;
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u32 x:6;
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u32 y:6;
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u32 n_blks:8;
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};
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static int tegra_p2u_power_off(struct phy *x)
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{
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return 0;
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}
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static int tegra_p2u_power_on(struct phy *x)
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{
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u32 val;
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struct tegra_p2u *phy = phy_get_drvdata(x);
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if (phy->enable_lm) {
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val = P2U_RX_MARGIN_SW_INT_EN_READINESS |
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P2U_RX_MARGIN_SW_INT_EN_MARGIN_START |
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P2U_RX_MARGIN_SW_INT_EN_MARGIN_CHANGE |
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P2U_RX_MARGIN_SW_INT_EN_MARGIN_STOP;
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writel(val, phy->base + P2U_RX_MARGIN_SW_INT_EN);
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}
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if (!phy->disable_uphy_rx_idle) {
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val = readl(phy->base + P2U_CONTROL_GEN1);
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val &= ~P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_EIOS;
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val |= P2U_CONTROL_GEN1_ENABLE_RXIDLE_ENTRY_ON_LINK_STATUS;
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writel(val, phy->base + P2U_CONTROL_GEN1);
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}
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val = readl(phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);
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val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
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val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
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writel(val, phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);
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val = readl(phy->base + P2U_PERIODIC_EQ_CTRL_GEN4);
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val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;
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writel(val, phy->base + P2U_PERIODIC_EQ_CTRL_GEN4);
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val = readl(phy->base + P2U_RX_DEBOUNCE_TIME);
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val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;
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val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
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writel(val, phy->base + P2U_RX_DEBOUNCE_TIME);
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return 0;
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}
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static int tegra_p2u_init(struct phy *x)
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{
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return 0;
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}
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static int tegra_p2u_exit(struct phy *x)
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{
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return 0;
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}
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static const struct phy_ops ops = {
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.init = tegra_p2u_init,
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.exit = tegra_p2u_exit,
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.power_on = tegra_p2u_power_on,
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.power_off = tegra_p2u_power_off,
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.owner = THIS_MODULE,
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};
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static int set_margin_control(u32 id, u32 ctrl_data)
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{
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struct mrq_uphy_request req;
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struct mrq_uphy_response resp;
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struct margin_ctrl ctrl;
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memcpy(&ctrl, &ctrl_data, sizeof(ctrl_data));
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req.lane = id;
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req.cmd = CMD_UPHY_PCIE_LANE_MARGIN_CONTROL;
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req.uphy_set_margin_control.en = ctrl.en;
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req.uphy_set_margin_control.clr = ctrl.clr;
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req.uphy_set_margin_control.x = ctrl.x;
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req.uphy_set_margin_control.y = ctrl.y;
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req.uphy_set_margin_control.nblks = ctrl.n_blks;
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return tegra_bpmp_send_receive(MRQ_UPHY, &req, sizeof(req),
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&resp, sizeof(resp));
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}
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static int get_margin_status(u32 id, u32 *val)
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{
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struct mrq_uphy_request req;
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struct mrq_uphy_response resp;
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int rc;
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req.lane = id;
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req.cmd = CMD_UPHY_PCIE_LANE_MARGIN_STATUS;
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rc = tegra_bpmp_send_receive(MRQ_UPHY, &req, sizeof(req), &resp,
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sizeof(resp));
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*val = resp.uphy_get_margin_status.status;
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return (rc < 0) ? rc : 0;
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}
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void rx_margin_work_fn(struct work_struct *work)
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{
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struct tegra_p2u *phy =
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container_of(work, struct tegra_p2u, rx_margin_work);
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unsigned long flags;
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u32 val;
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int ret;
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u8 state;
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do {
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spin_lock_irqsave(&phy->next_state_lock, flags);
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state = phy->next_state;
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spin_unlock_irqrestore(&phy->next_state_lock, flags);
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switch (state) {
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case RX_MARGIN_START_CHANGE:
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case RX_MARGIN_STOP:
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val = readl(phy->base + P2U_RX_MARGIN_CTRL);
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ret = set_margin_control(phy->id, val);
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if (ret) {
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dev_err(phy->dev,
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"MARGIN_SET BPMP-FW SEND ERR\n");
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break;
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}
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val = readl(phy->base + P2U_RX_MARGIN_SW_STATUS);
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val |= P2U_RX_MARGIN_SW_STATUS_MARGIN_SW_READY;
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val |= P2U_RX_MARGIN_SW_STATUS_MARGIN_READY;
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val |= P2U_RX_MARGIN_SW_STATUS_PHY_MARGIN_STATUS;
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val |= P2U_RX_MARGIN_SW_STATUS_PHY_MARGIN_ERROR_STATUS;
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writel(val, phy->base + P2U_RX_MARGIN_SW_STATUS);
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udelay(10);
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if (state != RX_MARGIN_STOP) {
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spin_lock_irqsave(&phy->next_state_lock, flags);
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phy->next_state = RX_MARGIN_GET_MARGIN;
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spin_unlock_irqrestore(&phy->next_state_lock,
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flags);
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continue;
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}
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case RX_MARGIN_GET_MARGIN:
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if (state != RX_MARGIN_STOP) {
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ret = get_margin_status(phy->id, &val);
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if (ret) {
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dev_err(phy->dev,
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"MARGIN_GET BPMP-FW RCV ERR\n");
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break;
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}
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writel(val & P2U_RX_MARGIN_STATUS_ERRORS_MASK,
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phy->base + P2U_RX_MARGIN_STATUS);
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}
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val = readl(phy->base + P2U_RX_MARGIN_SW_STATUS);
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val |= P2U_RX_MARGIN_SW_STATUS_MARGIN_SW_READY;
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val |= P2U_RX_MARGIN_SW_STATUS_MARGIN_READY;
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val &= ~P2U_RX_MARGIN_SW_STATUS_PHY_MARGIN_STATUS;
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val |= P2U_RX_MARGIN_SW_STATUS_PHY_MARGIN_ERROR_STATUS;
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writel(val, phy->base + P2U_RX_MARGIN_SW_STATUS);
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if (state != RX_MARGIN_STOP) {
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msleep(20);
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continue;
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} else {
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return;
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}
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break;
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default:
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dev_err(phy->dev, "MARGIN INVALID STATE\n");
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return;
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};
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} while (1);
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}
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static irqreturn_t tegra_p2u_irq_handler(int irq, void *arg)
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{
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struct tegra_p2u *phy = (struct tegra_p2u *)arg;
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unsigned long flags;
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u32 val = 0;
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val = readl(phy->base + P2U_RX_MARGIN_SW_INT);
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writel(val, phy->base + P2U_RX_MARGIN_SW_INT);
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switch (val & P2U_RX_MARGIN_SW_INT_MASK) {
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case P2U_RX_MARGIN_SW_INT_READINESS:
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dev_dbg(phy->dev, "Rx_Margin_intr : READINESS\n");
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val = readl(phy->base + P2U_RX_MARGIN_SW_STATUS);
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val |= P2U_RX_MARGIN_SW_STATUS_MARGIN_SW_READY;
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val |= P2U_RX_MARGIN_SW_STATUS_MARGIN_READY;
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writel(val, phy->base + P2U_RX_MARGIN_SW_STATUS);
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/* Write N_BLKS with any value between {0x80, 0xFF} */
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val = readl(phy->base + P2U_RX_MARGIN_CTRL);
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val &= P2U_RX_MARGIN_CTRL_N_BLKS_MASK;
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val |= (N_BLKS_COUNT << P2U_RX_MARGIN_CTRL_N_BLKS_SHIFT);
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writel(val, phy->base + P2U_RX_MARGIN_CTRL);
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break;
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case P2U_RX_MARGIN_SW_INT_MARGIN_STOP:
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dev_dbg(phy->dev, "Rx_Margin_intr : MARGIN_STOP\n");
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spin_lock_irqsave(&phy->next_state_lock, flags);
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phy->next_state = RX_MARGIN_STOP;
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spin_unlock_irqrestore(&phy->next_state_lock, flags);
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break;
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case P2U_RX_MARGIN_SW_INT_MARGIN_CHANGE:
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case (P2U_RX_MARGIN_SW_INT_MARGIN_CHANGE |
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P2U_RX_MARGIN_SW_INT_MARGIN_START):
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dev_dbg(phy->dev, "Rx_Margin_intr : MARGIN_CHANGE\n");
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spin_lock_irqsave(&phy->next_state_lock, flags);
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phy->next_state = RX_MARGIN_START_CHANGE;
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spin_unlock_irqrestore(&phy->next_state_lock, flags);
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/* fallthrough */
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case P2U_RX_MARGIN_SW_INT_MARGIN_START:
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dev_dbg(phy->dev, "Rx_Margin_intr : MARGIN_START\n");
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schedule_work(&phy->rx_margin_work);
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break;
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default:
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dev_err(phy->dev, "INVALID Rx_Margin_intr : 0x%x\n", val);
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break;
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}
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return IRQ_HANDLED;
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}
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static int tegra_p2u_probe(struct platform_device *pdev)
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{
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struct tegra_p2u *phy;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct resource *res;
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u32 val;
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int irq, ret = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
|
||
|
|
|
||
|
|
phy->dev = dev;
|
||
|
|
|
||
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
|
||
|
|
phy->base = devm_ioremap_resource(dev, res);
|
||
|
|
if (IS_ERR(phy->base))
|
||
|
|
return PTR_ERR(phy->base);
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, phy);
|
||
|
|
|
||
|
|
generic_phy = devm_phy_create(dev, NULL, &ops);
|
||
|
|
if (IS_ERR(generic_phy))
|
||
|
|
return PTR_ERR(generic_phy);
|
||
|
|
|
||
|
|
phy_set_drvdata(generic_phy, phy);
|
||
|
|
|
||
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||
|
|
if (IS_ERR(phy_provider))
|
||
|
|
return PTR_ERR(phy_provider);
|
||
|
|
|
||
|
|
ret = of_property_read_u32(dev->of_node, "nvidia,uphy-id", &val);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "uphy-id is missing\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
phy->id = val;
|
||
|
|
|
||
|
|
phy->enable_lm = of_property_read_bool(dev->of_node,
|
||
|
|
"nvidia,enable-lm");
|
||
|
|
|
||
|
|
phy->disable_uphy_rx_idle =
|
||
|
|
of_property_read_bool(dev->of_node,
|
||
|
|
"nvidia,disable-uphy-rx-idle");
|
||
|
|
|
||
|
|
spin_lock_init(&phy->next_state_lock);
|
||
|
|
INIT_WORK(&phy->rx_margin_work, rx_margin_work_fn);
|
||
|
|
|
||
|
|
irq = platform_get_irq_byname(pdev, "intr");
|
||
|
|
if (!irq) {
|
||
|
|
dev_err(dev, "failed to get intr interrupt\n");
|
||
|
|
return irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = devm_request_irq(&pdev->dev, irq, tegra_p2u_irq_handler, 0,
|
||
|
|
"tegra-p2u-intr", phy);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "failed to request \"intr\" irq\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tegra_p2u_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id tegra_p2u_id_table[] = {
|
||
|
|
{
|
||
|
|
.compatible = "nvidia,phy-p2u",
|
||
|
|
},
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, tegra_p2u_id_table);
|
||
|
|
|
||
|
|
static struct platform_driver tegra_p2u_driver = {
|
||
|
|
.probe = tegra_p2u_probe,
|
||
|
|
.remove = tegra_p2u_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "tegra-p2u",
|
||
|
|
.of_match_table = tegra_p2u_id_table,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(tegra_p2u_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
|
||
|
|
MODULE_DESCRIPTION("Nvidia Tegra PIPE_To_UPHY phy driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|