150 lines
4.0 KiB
C
150 lines
4.0 KiB
C
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/*
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* drivers/platform/tegra/iomap_t18x.h
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/* Temporary address map file before DT takes place */
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#ifndef PLATFORM_TEGRA_IOMAP_H
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#define PLATFORM_TEGRA_IOMAP_H
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#undef TEGRA_HOST1X_BASE
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#undef TEGRA_VI_BASE
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#undef TEGRA_CSI_BASE
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#undef TEGRA_NVCSI_BASE
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#undef TEGRA_ISP_BASE
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#undef TEGRA_ISPB_BASE
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#undef TEGRA_VII2C_BASE
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#undef TEGRA_I2C2_BASE
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#undef TEGRA_I2C3_BASE
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#undef TEGRA_I2C4_BASE
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#undef TEGRA_DISPLAY_BASE
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#undef TEGRA_DSI_BASE
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#undef TEGRA_VIC_BASE
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#undef TEGRA_NVENC_BASE
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#undef TEGRA_NVDEC_BASE
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#undef TEGRA_NVJPG_BASE
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#undef TEGRA_DSIB_BASE
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#undef TEGRA_TSEC_BASE
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#undef TEGRA_TSECB_BASE
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#undef TEGRA_SOR_BASE
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#undef TEGRA_SOR1_BASE
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#undef TEGRA_DPAUX_BASE
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#undef TEGRA_DPAUX1_BASE
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#undef TEGRA_MC0_BASE
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#undef TEGRA_MC1_BASE
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#undef TEGRA_EMC0_BASE
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#undef TEGRA_EMC1_BASE
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#undef TEGRA_SATA_BASE
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#undef TEGRA_VI_SIZE
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#undef TEGRA_CSI_SIZE
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#undef TEGRA_NVCSI_SIZE
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#undef TEGRA_ISP_SIZE
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#undef TEGRA_ISPB_SIZE
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#undef TEGRA_VII2C_SIZE
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#undef TEGRA_I2C2_SIZE
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#undef TEGRA_I2C3_SIZE
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#undef TEGRA_I2C4_SIZE
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#undef TEGRA_DISPLAY_SIZE
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#undef TEGRA_DSI_SIZE
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#undef TEGRA_VIC_SIZE
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#undef TEGRA_NVENC_SIZE
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#undef TEGRA_NVDEC_SIZE
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#undef TEGRA_NVJPG_SIZE
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#undef TEGRA_DSIB_SIZE
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#undef TEGRA_TSEC_SIZE
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#undef TEGRA_TSECB_SIZE
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#undef TEGRA_SOR_SIZE
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#undef TEGRA_SOR1_SIZE
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#undef TEGRA_DPAUX_SIZE
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#undef TEGRA_DPAUX1_SIZE
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#undef TEGRA_MC0_SIZE
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#undef TEGRA_MC1_SIZE
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#undef TEGRA_EMC0_SIZE
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#undef TEGRA_EMC1_SIZE
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#undef TEGRA_SATA_SIZE
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#define TEGRA_HOST1X_BASE 0X3de00000
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#define TEGRA_HOST1x_SIZE SZ_256K
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#define TEGRA_VI_BASE 0x54700000
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#define TEGRA_CSI_BASE 0x54080000
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#define TEGRA_NVCSI_BASE 0x540c0000
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#define TEGRA_ISP_BASE 0x54600000
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#define TEGRA_ISPB_BASE 0x54680000
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#define TEGRA_VII2C_BASE 0x546c0000
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#define TEGRA_I2C2_BASE 0x00000000
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#define TEGRA_I2C3_BASE 0x00010000
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#define TEGRA_I2C4_BASE 0x00020000
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#define TEGRA_DISPLAY_BASE 0x54200000
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#define TEGRA_DSI_BASE 0x54300000
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#define TEGRA_VIC_BASE 0x54340000
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#define TEGRA_NVENC_BASE 0x544c0000
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#define TEGRA_NVDEC_BASE 0x54480000
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#define TEGRA_NVJPG_BASE 0x54380000
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#define TEGRA_DSIB_BASE 0x54400000
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#define TEGRA_TSEC_BASE 0x54500000
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#define TEGRA_TSECB_BASE 0x54100000
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#define TEGRA_SOR_BASE 0x54540000
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#define TEGRA_SOR1_BASE 0x54580000
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#define TEGRA_DPAUX_BASE 0x545c0000
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#define TEGRA_DPAUX1_BASE 0x54040000
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#define TEGRA_VI_SIZE SZ_1M
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#define TEGRA_CSI_SIZE SZ_256K
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#define TEGRA_NVCSI_SIZE SZ_256K
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#define TEGRA_ISP_SIZE SZ_256K
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#define TEGRA_ISPB_SIZE SZ_256K
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#define TEGRA_VII2C_SIZE SZ_256K
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#define TEGRA_I2C2_SIZE SZ_64K
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#define TEGRA_I2C3_SIZE SZ_64K
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#define TEGRA_I2C4_SIZE SZ_64K
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#define TEGRA_DISPLAY_SIZE SZ_256K
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#define TEGRA_DSI_SIZE SZ_256K
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#define TEGRA_VIC_SIZE SZ_256K
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#define TEGRA_NVENC_SIZE SZ_256K
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#define TEGRA_NVDEC_SIZE SZ_256K
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#define TEGRA_NVJPG_SIZE SZ_256K
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#define TEGRA_DSIB_SIZE SZ_256K
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#define TEGRA_TSEC_SIZE SZ_256K
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#define TEGRA_TSECB_SIZE SZ_256K
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#define TEGRA_SOR_SIZE SZ_256K
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#define TEGRA_SOR1_SIZE SZ_256K
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#define TEGRA_DPAUX_SIZE SZ_256K
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#define TEGRA_DPAUX1_SIZE SZ_256K
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#define TEGRA_MC0_BASE 0x7001c000
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#define TEGRA_MC1_BASE 0x7001d000
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#define TEGRA_EMC0_BASE 0x7001e000
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#define TEGRA_EMC1_BASE 0x7001f000
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#define TEGRA_SATA_BASE 0x70020000
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#define TEGRA_MC0_SIZE SZ_4K
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#define TEGRA_MC1_SIZE SZ_4K
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#define TEGRA_EMC0_SIZE SZ_4K
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#define TEGRA_EMC1_SIZE SZ_4K
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#define TEGRA_SATA_SIZE SZ_4K
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#endif
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