467 lines
11 KiB
C
467 lines
11 KiB
C
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/*
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* arch/arm/mach-tegra/isomgr-pre_t19x.c
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#define pr_fmt(fmt) "%s(): " fmt, __func__
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#ifdef CONFIG_COMMON_CLK
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#include <linux/platform/tegra/bwmgr_mc.h>
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#else
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#include <linux/platform/tegra/mc.h>
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#include <linux/clk.h>
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#include <linux/platform/tegra/clock.h>
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#endif
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include <linux/platform/tegra/isomgr.h>
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#include <linux/io.h>
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#include <soc/tegra/chip-id.h>
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/* This file contains platform specific isomgr
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* code for all chips prior to T194.
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*/
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#define ISOMGR_DEBUG 1
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#if ISOMGR_DEBUG
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#define SANITY_CHECK_AVAIL_BW() { \
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int t = 0; \
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int idx = 0; \
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for (idx = 0; idx < TEGRA_ISO_CLIENT_COUNT; idx++) { \
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if (isomgr_clients[idx].real_bw >= \
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isomgr_clients[idx].margin_bw) \
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t += isomgr_clients[idx].real_bw; \
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else \
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t += isomgr_clients[idx].margin_bw; \
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} \
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if (t + isomgr.avail_bw != isomgr.max_iso_bw) { \
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pr_err("bw mismatch, line=%d\n", __LINE__); \
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pr_err("t+isomgr.avail_bw=%d, isomgr.max_iso_bw=%d\n", \
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t + isomgr.avail_bw, isomgr.max_iso_bw); \
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return false; \
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} \
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}
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#else
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#define SANITY_CHECK_AVAIL_BW()
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#endif
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static int iso_bw_percentage = 100;
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static struct isoclient_info tegra_null_isoclients[] = {
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/* This must be last entry*/
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{
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.client = TEGRA_ISO_CLIENT_COUNT,
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.name = NULL,
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},
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};
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static struct isoclient_info tegra11x_isoclients[] = {
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{
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.client = TEGRA_ISO_CLIENT_DISP_0,
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.name = "disp_0",
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.dev_name = "tegradc.0",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_DISP_1,
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.name = "disp_1",
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.dev_name = "tegradc.1",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_VI_0,
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.name = "vi_0",
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.dev_name = "vi",
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.emc_clk_name = "emc",
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},
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/* This must be last entry*/
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{
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.client = TEGRA_ISO_CLIENT_COUNT,
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.name = NULL,
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},
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};
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static struct isoclient_info tegra14x_isoclients[] = {
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{
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.client = TEGRA_ISO_CLIENT_DISP_0,
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.name = "disp_0",
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.dev_name = "tegradc.0",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_DISP_1,
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.name = "disp_1",
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.dev_name = "tegradc.1",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_VI_0,
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.name = "vi_0",
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.dev_name = "vi",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_BBC_0,
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.name = "bbc_0",
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.dev_name = "tegra_bb.0",
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.emc_clk_name = "emc_bw",
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},
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/* This must be last entry*/
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{
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.client = TEGRA_ISO_CLIENT_COUNT,
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.name = NULL,
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},
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};
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static struct isoclient_info tegra12x_isoclients[] = {
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{
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.client = TEGRA_ISO_CLIENT_DISP_0,
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.name = "disp_0",
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.dev_name = "tegradc.0",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_DISP_1,
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.name = "disp_1",
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.dev_name = "tegradc.1",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_VI_0,
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.name = "vi_0",
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.dev_name = "tegra_vi",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_ISP_A,
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.name = "isp_a",
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.dev_name = "tegra_isp.0",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_ISP_B,
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.name = "isp_b",
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.dev_name = "tegra_isp.1",
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.emc_clk_name = "emc",
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},
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{
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.client = TEGRA_ISO_CLIENT_TEGRA_CAMERA,
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.name = "tegra_camera",
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.dev_name = "tegra_camera_ctrl",
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.emc_clk_name = "iso.emc",
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},
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/* This must be last entry*/
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{
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.client = TEGRA_ISO_CLIENT_COUNT,
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.name = NULL,
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},
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};
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static struct isoclient_info tegra21x_isoclients[] = {
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{
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.client = TEGRA_ISO_CLIENT_DISP_0,
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.name = "disp_0",
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.dev_name = "tegradc.0",
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.emc_clk_name = "emc",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_DISP0,
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},
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{
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.client = TEGRA_ISO_CLIENT_DISP_1,
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.name = "disp_1",
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.dev_name = "tegradc.1",
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.emc_clk_name = "emc",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_DISP1,
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},
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{
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.client = TEGRA_ISO_CLIENT_VI_0,
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.name = "vi_0",
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.dev_name = "tegra_vi",
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.emc_clk_name = "emc",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_VI,
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},
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{
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.client = TEGRA_ISO_CLIENT_ISP_A,
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.name = "isp_a",
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.dev_name = "tegra_isp.0",
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.emc_clk_name = "emc",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_ISPA,
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},
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{
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.client = TEGRA_ISO_CLIENT_ISP_B,
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.name = "isp_b",
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.dev_name = "tegra_isp.1",
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.emc_clk_name = "emc",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_ISPB,
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},
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{
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.client = TEGRA_ISO_CLIENT_TEGRA_CAMERA,
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.name = "tegra_camera",
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.dev_name = "tegra_camera_ctrl",
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.emc_clk_name = "iso.emc",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_CAMERA,
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},
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/* This must be last entry*/
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{
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.client = TEGRA_ISO_CLIENT_COUNT,
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.name = NULL,
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},
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};
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static struct isoclient_info tegra18x_isoclients[] = {
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{
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.client = TEGRA_ISO_CLIENT_DISP_0,
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.name = "disp_0",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_DISP0,
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},
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{
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.client = TEGRA_ISO_CLIENT_DISP_1,
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.name = "disp_1",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_DISP1,
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},
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{
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.client = TEGRA_ISO_CLIENT_DISP_2,
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.name = "disp_2",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_DISP2,
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},
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{
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.client = TEGRA_ISO_CLIENT_ISP_A,
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.name = "isp_a",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_ISPA,
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},
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{
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.client = TEGRA_ISO_CLIENT_TEGRA_CAMERA,
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.name = "camera",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_CAMERA,
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},
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{
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.client = TEGRA_ISO_CLIENT_APE_ADMA,
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.name = "ape_adma",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_APE_ADMA,
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},
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{
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.client = TEGRA_ISO_CLIENT_EQOS,
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.name = "eqos",
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.bwmgr_id = TEGRA_BWMGR_CLIENT_EQOS,
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},
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/* This must be last entry*/
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{
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.client = TEGRA_ISO_CLIENT_COUNT,
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.name = NULL,
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},
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};
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static struct isoclient_info *get_iso_client_info(int *length)
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{
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enum tegra_chipid cid;
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struct isoclient_info *cinfo;
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int i, len;
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cid = tegra_get_chip_id();
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switch (cid) {
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case TEGRA114:
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cinfo = tegra11x_isoclients;
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len = ARRAY_SIZE(tegra11x_isoclients);
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iso_bw_percentage = 50;
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for (i = 0; i < TEGRA_ISO_CLIENT_COUNT; i++)
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isomgr_clients[i].limit_bw_percentage = 100;
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break;
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case TEGRA148:
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cinfo = tegra14x_isoclients;
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len = ARRAY_SIZE(tegra14x_isoclients);
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iso_bw_percentage = 50;
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for (i = 0; i < TEGRA_ISO_CLIENT_COUNT; i++)
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isomgr_clients[i].limit_bw_percentage = 100;
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break;
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case TEGRA124:
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case TEGRA132:
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cinfo = tegra12x_isoclients;
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len = ARRAY_SIZE(tegra12x_isoclients);
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iso_bw_percentage = 50;
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for (i = 0; i < TEGRA_ISO_CLIENT_COUNT; i++)
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isomgr_clients[i].limit_bw_percentage = 100;
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break;
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case TEGRA210:
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cinfo = tegra21x_isoclients;
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iso_bw_percentage = 45; /* Hack: Should be determined based on
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* DRAM type
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*/
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len = ARRAY_SIZE(tegra21x_isoclients);
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for (i = 0; i < TEGRA_ISO_CLIENT_COUNT; i++)
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isomgr_clients[i].limit_bw_percentage = 100;
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break;
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case TEGRA186:
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cinfo = tegra18x_isoclients;
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len = ARRAY_SIZE(tegra18x_isoclients);
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for (i = 0; i < TEGRA_ISO_CLIENT_COUNT; i++) {
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if (i == TEGRA_ISO_CLIENT_TEGRA_CAMERA)
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isomgr_clients[i].limit_bw_percentage = 10;
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else
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isomgr_clients[i].limit_bw_percentage = 100;
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}
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break;
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default:
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cinfo = tegra_null_isoclients;
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len = 0;
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break;
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}
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if (length)
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*length = len;
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return cinfo;
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}
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static void pre_t19x_iso_plat_init(void)
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{
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unsigned int max_emc_clk;
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unsigned int max_emc_bw;
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if (!isomgr.max_iso_bw) {
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#ifdef CONFIG_COMMON_CLK
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max_emc_clk = tegra_bwmgr_get_max_emc_rate() / 1000;
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max_emc_bw = bwmgr_freq_to_bw(max_emc_clk);
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isomgr.max_iso_bw = max_emc_bw *
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bwmgr_iso_bw_percentage_max() / 100;
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#else
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/* With DVFS disabled, bus children cannot get real
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* max emc freq supported Only the root parent EMC
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* node is set to max possible rate
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*/
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max_emc_clk = clk_round_rate(clk_get_parent(isomgr.emc_clk),
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ULONG_MAX) / 1000;
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max_emc_bw = tegra_emc_freq_req_to_bw(max_emc_clk);
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/* ISO clients can use iso_bw_percentage of max emc bw. */
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isomgr.max_iso_bw = max_emc_bw * iso_bw_percentage / 100;
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#endif
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pr_info("iso emc max clk=%dKHz\n", max_emc_clk);
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pr_info("max_iso_bw=%dKB\n", isomgr.max_iso_bw);
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isomgr.avail_bw = isomgr.max_iso_bw;
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}
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}
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static void pre_t19x_iso_plat_unregister(struct isomgr_client *cp)
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{
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if (cp->real_bw > cp->margin_bw)
|
||
|
|
isomgr.avail_bw += cp->real_bw;
|
||
|
|
else
|
||
|
|
isomgr.avail_bw += cp->margin_bw;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool pre_t19x_iso_plat_reserve(struct isomgr_client *cp, u32 bw,
|
||
|
|
enum tegra_iso_client client)
|
||
|
|
{
|
||
|
|
u64 bw_check;
|
||
|
|
u32 max_emc_bw;
|
||
|
|
|
||
|
|
if (bw <= cp->margin_bw)
|
||
|
|
goto bw_limit_check;
|
||
|
|
|
||
|
|
if (bw > cp->dedi_bw &&
|
||
|
|
bw > isomgr.avail_bw + cp->real_bw - isomgr.sleep_bw)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
bw_limit_check:
|
||
|
|
/* During reserve, check if BW request is within limit_bw_percentage%
|
||
|
|
* of max emc bw. Using max emc bw to find if the request is possible
|
||
|
|
* when we raise the freq to max possible value. If not, the reserve
|
||
|
|
* call will fail
|
||
|
|
*/
|
||
|
|
#ifdef CONFIG_COMMON_CLK
|
||
|
|
max_emc_bw = bwmgr_freq_to_bw(tegra_bwmgr_get_max_emc_rate() / 1000);
|
||
|
|
#else
|
||
|
|
max_emc_bw = tegra_emc_freq_req_to_bw(
|
||
|
|
clk_round_rate(clk_get_parent(isomgr.emc_clk), ULONG_MAX)
|
||
|
|
/ 1000);
|
||
|
|
#endif
|
||
|
|
bw_check = ((u64)max_emc_bw * (u64)(cp->limit_bw_percentage) / 100);
|
||
|
|
if (bw > bw_check)
|
||
|
|
return false;
|
||
|
|
else
|
||
|
|
return true;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool pre_t19x_iso_plat_realize(struct isomgr_client *cp)
|
||
|
|
{
|
||
|
|
s32 delta_bw = 0;
|
||
|
|
|
||
|
|
if (cp->margin_bw < cp->real_bw)
|
||
|
|
isomgr.avail_bw += cp->real_bw - cp->margin_bw;
|
||
|
|
|
||
|
|
cp->real_bw = 0;
|
||
|
|
cp->realize = true;
|
||
|
|
|
||
|
|
if (unlikely(isomgr.avail_bw > isomgr.max_iso_bw)) {
|
||
|
|
pr_err("isomgr: iso_plat_realize: avail_bw > max_iso_bw\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (cp->rsvd_bw <= cp->margin_bw) {
|
||
|
|
if (unlikely(cp->sleep_bw)) {
|
||
|
|
pr_err
|
||
|
|
("isomgr_realize: rsvd_bw < margin_bw, sleep_bw = 1\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
cp->real_bw = cp->rsvd_bw; /* reservation has been realized */
|
||
|
|
cp->real_mf = cp->rsvd_mf; /* minimum frequency realized */
|
||
|
|
} else if (cp->rsvd_bw <= isomgr.avail_bw + cp->margin_bw) {
|
||
|
|
delta_bw = cp->rsvd_bw - cp->margin_bw;
|
||
|
|
isomgr.avail_bw -= delta_bw;
|
||
|
|
cp->real_bw = cp->rsvd_bw; /* reservation has been realized */
|
||
|
|
cp->real_mf = cp->rsvd_mf; /* minimum frequency realized */
|
||
|
|
if (cp->sleep_bw) {
|
||
|
|
isomgr.sleep_bw -= delta_bw;
|
||
|
|
cp->sleep_bw -= delta_bw;
|
||
|
|
if (unlikely(cp->sleep_bw)) {
|
||
|
|
pr_err
|
||
|
|
("isomgr:rsvd_bw < margin_bw, sleep_bw = 1\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (unlikely(isomgr.avail_bw < 0)) {
|
||
|
|
pr_err("isomgr: iso_plat_realize: avail_bw < 0\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
SANITY_CHECK_AVAIL_BW();
|
||
|
|
} else {
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool pre_t19x_iso_plat_register(u32 dedi_bw, enum tegra_iso_client client)
|
||
|
|
{
|
||
|
|
if (unlikely(dedi_bw > isomgr.max_iso_bw - isomgr.dedi_bw)) {
|
||
|
|
pr_err("iso bandwidth %uKB is not available, client %s\n",
|
||
|
|
dedi_bw, cname[client]);
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct isomgr_ops isomgr_ops_pre_t19x = {
|
||
|
|
.isomgr_plat_init = pre_t19x_iso_plat_init,
|
||
|
|
.isomgr_plat_register = pre_t19x_iso_plat_register,
|
||
|
|
.isomgr_plat_unregister = pre_t19x_iso_plat_unregister,
|
||
|
|
.isomgr_plat_reserve = pre_t19x_iso_plat_reserve,
|
||
|
|
.isomgr_plat_realize = pre_t19x_iso_plat_realize,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct isomgr_ops *pre_t19x_isomgr_init(void)
|
||
|
|
{
|
||
|
|
isoclient_info = get_iso_client_info(&isoclients);
|
||
|
|
return &isomgr_ops_pre_t19x;
|
||
|
|
}
|