456 lines
12 KiB
C
456 lines
12 KiB
C
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/*
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* Tegra 18x SoC-specific mcerr code.
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*
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* Copyright (c) 2015-2018, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#define pr_fmt(fmt) "mc-err: " fmt
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#include <linux/bitops.h>
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#include <linux/of.h>
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#include <linux/platform/tegra/mc-regs-t18x.h>
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#include <linux/platform/tegra/mcerr.h>
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#include <dt-bindings/memory/tegra-swgroup.h>
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#include <linux/interrupt.h>
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/*** Auto generated by `mcp.pl'. Do not modify! ***/
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static struct mc_client mc_clients[] = {
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client("ptc", "csr_ptcr", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("afi", "csr_afir", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("hda", "csr_hdar", INVALID),
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client("hc", "csr_host1xdmar", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("nvenc", "csr_nvencsrd", INVALID),
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dummy_client,
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dummy_client,
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client("sata", "csr_satar", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("mpcore", "csr_mpcorer", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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client("nvenc", "csw_nvencswr", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("afi", "csw_afiw", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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client("hda", "csw_hdaw", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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client("mpcore", "csw_mpcorew", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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client("sata", "csw_sataw", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("isp2", "csr_ispra", INVALID),
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dummy_client,
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client("isp2", "csw_ispwa", INVALID),
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client("isp2", "csw_ispwb", INVALID),
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dummy_client,
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dummy_client,
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client("xusb_host", "csr_xusb_hostr", INVALID),
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client("xusb_host", "csw_xusb_hostw", INVALID),
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client("xusb_dev", "csr_xusb_devr", INVALID),
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client("xusb_dev", "csw_xusb_devw", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("tsec", "csr_tsecsrd", INVALID),
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client("tsec", "csw_tsecswr", INVALID),
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dummy_client,
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dummy_client,
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client("gpu", "csr_gpusrd", INVALID),
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client("gpu", "csw_gpuswr", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("sdmmc1a", "csr_sdmmcra", INVALID),
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client("sdmmc2a", "csr_sdmmcraa", INVALID),
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client("sdmmc3a", "csr_sdmmcr", INVALID),
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client("sdmmc4a", "csr_sdmmcrab", INVALID),
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client("sdmmc1a", "csw_sdmmcwa", INVALID),
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client("sdmmc2a", "csw_sdmmcwaa", INVALID),
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client("sdmmc3a", "csw_sdmmcw", INVALID),
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client("sdmmc4a", "csw_sdmmcwab", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("vic", "csr_vicsrd", INVALID),
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client("vic", "csw_vicswr", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("vi", "csw_viw", INVALID),
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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dummy_client,
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client("nvdec", "csr_nvdecsrd", INVALID),
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client("nvdec", "csw_nvdecswr", INVALID),
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client("ape", "csr_aper", INVALID),
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client("ape", "csw_apew", INVALID),
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dummy_client,
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dummy_client,
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client("nvjpg", "csr_nvjpgsrd", INVALID),
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client("nvjpg", "csw_nvjpgswr", INVALID),
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client("se", "csr_sesrd", INVALID),
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client("se", "csw_seswr", INVALID),
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dummy_client,
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dummy_client,
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client("etr", "csr_etrr", INVALID),
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client("etr", "csw_etrw", INVALID),
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client("tsecb", "csr_tsecsrdb", INVALID),
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client("tsecb", "csw_tsecswrb", INVALID),
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client("gpu", "csr_gpusrd2", INVALID),
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client("gpu", "csw_gpuswr2", INVALID),
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dummy_client,
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dummy_client,
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client("axis", "csr_axisr", INVALID),
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client("axis", "csw_axisw", INVALID),
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client("eqos", "csr_eqosr", INVALID),
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client("eqos", "csw_eqosw", INVALID),
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client("ufshc", "csr_ufshcr", INVALID),
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client("ufshc", "csw_ufshcw", INVALID),
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client("nvdisplay", "csr_nvdisplayr", INVALID),
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client("bpmp", "csr_bpmpr", INVALID),
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client("bpmp", "csw_bpmpw", INVALID),
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client("bpmp", "csr_bpmpdmar", INVALID),
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client("bpmp", "csw_bpmpdmaw", INVALID),
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client("aon", "csr_aonr", INVALID),
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client("aon", "csw_aonw", INVALID),
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client("aon", "csr_aondmar", INVALID),
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client("aon", "csw_aondmaw", INVALID),
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client("sce", "csr_scer", INVALID),
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client("sce", "csw_scew", INVALID),
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client("sce", "csr_scedmar", INVALID),
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client("sce", "csw_scedmaw", INVALID),
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client("ape", "csr_apedmar", INVALID),
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client("ape", "csw_apedmaw", INVALID),
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client("nvdisplay", "csr_nvdisplayr1", INVALID),
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client("vic", "csr_vicsrd1", INVALID),
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client("nvdec", "csr_nvdecsrd1", INVALID),
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};
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static int mc_client_last = ARRAY_SIZE(mc_clients) - 1;
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/*** Done. ***/
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static const char *t186_intr_info[] = {
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NULL, /* Bit 0 */
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NULL,
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NULL,
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NULL,
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NULL, /* Bit 4 */
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NULL,
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"decerr-emem",
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NULL,
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"secerr", /* Bit 8 */
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"arb-emem",
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NULL,
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NULL,
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"decerr-vpr", /* Bit 12 */
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"decerr-sec",
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NULL,
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NULL,
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"decerr-mts", /* Bit 16 */
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"decerr-gsc",
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"scrub-ecc",
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"wcam-err",
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NULL, /* Bit 20 */
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NULL,
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NULL,
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NULL,
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NULL, /* Bit 24 */
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NULL,
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NULL,
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NULL,
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NULL, /* Bit 28 */
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NULL,
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NULL,
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NULL,
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};
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#define MC_INT_DECERR_MTS (1<<16)
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#define MC_INT_WCAM_ERR (1<<19)
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/* hub common int status */
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#define MC_HUBC_INT_SCRUB_ECC_WR_ACK (1 << 0)
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/* reported in MC_INTSTATUS_0 */
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static const struct mc_error hub_mc_errors[] = {
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MC_ERR(MC_INT_DECERR_EMEM,
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"EMEM address decode error",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_SECURITY_VIOLATION,
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"non secure access to secure region",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_DECERR_VPR,
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"MC request violates VPR requirements",
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E_VPR, MC_ERR_VPR_STATUS, MC_ERR_VPR_ADR),
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MC_ERR(MC_INT_SECERR_SEC,
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"MC request violated SEC carveout requirements",
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0, MC_ERR_SEC_STATUS, MC_ERR_SEC_ADR),
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MC_ERR(MC_INT_DECERR_MTS,
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"MTS carveout access violation",
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0, MC_ERR_MTS_STATUS, MC_ERR_MTS_ADR),
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MC_ERR(MC_INT_DECERR_GENERALIZED_CARVEOUT,
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"GSC access violation", 0,
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MC_ERR_GENERALIZED_CARVEOUT_STATUS,
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MC_ERR_GENERALIZED_CARVEOUT_ADR),
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/* combination interrupts */
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MC_ERR(MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION,
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"non secure access to secure region",
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0, MC_ERR_STATUS, MC_ERR_ADR),
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MC_ERR(MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_EMEM,
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"EMEM GSC access violation", 0,
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MC_ERR_GENERALIZED_CARVEOUT_STATUS,
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MC_ERR_GENERALIZED_CARVEOUT_ADR),
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/* NULL terminate. */
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MC_ERR(0, NULL, 0, 0, 0),
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};
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/* reported in MC_CH_INTSTATUS_0 */
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static const struct mc_error ch_mc_errors[] = {
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MC_ERR(MC_INT_WCAM_ERR, "WCAM error", E_TWO_STATUS,
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MC_WCAM_IRQ_P0_STATUS0,
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MC_WCAM_IRQ_P1_STATUS0),
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/* NULL terminate. */
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MC_ERR(0, NULL, 0, 0, 0),
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};
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/* reported in MC_HUBC_INTSTATUS_0 */
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static const struct mc_error hubc_mc_errors[] = {
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MC_ERR(MC_HUBC_INT_SCRUB_ECC_WR_ACK,
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"ECC scrub complete", E_NO_STATUS, 0, 0),
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/* NULL terminate. */
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MC_ERR(0, NULL, 0, 0, 0),
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};
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enum {
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INTSTATUS_CH0 = 0,
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INTSTATUS_CH1 = 1,
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INTSTATUS_CH2 = 2,
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INTSTATUS_CH3 = 3,
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INTSTATUS_HUB0 = 16,
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INTSTATUS_HUB1 = 17,
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INTSTATUS_HUBC = 24,
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};
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#define MC_INTSTATUS_CLEAR 0x00033340
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#define MC_CH_INTSTATUS_CLEAR 0x00080200
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#define MC_HUBC_INTSTATUS_CLEAR 0x00000001
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#define MC_GLOBAL_INTSTATUS_CLEAR 0x0103000F
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static void clear_interrupt(unsigned int irq)
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{
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mc_writel(MC_INTSTATUS_CLEAR, MC_INTSTATUS);
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mc_writel(MC_CH_INTSTATUS_CLEAR, MC_CH_INTSTATUS);
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mc_writel(MC_HUBC_INTSTATUS_CLEAR, MC_HUBC_INTSTATUS);
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mc_writel(MC_GLOBAL_INTSTATUS_CLEAR, MC_GLOBAL_INTSTATUS);
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}
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static void log_fault(int src_chan, const struct mc_error *fault)
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{
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phys_addr_t addr;
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struct mc_client *client;
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u32 status, write, secure, client_id;
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if (fault->flags & E_VPR)
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mcerr_pr("vpr base=%x:%x, size=%x, ctrl=%x, override:(%x, %x, %x, %x)\n",
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mc_readl(MC_VIDEO_PROTECT_BOM_ADR_HI),
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mc_readl(MC_VIDEO_PROTECT_BOM),
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mc_readl(MC_VIDEO_PROTECT_SIZE_MB),
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mc_readl(MC_VIDEO_PROTECT_REG_CTRL),
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mc_readl(MC_VIDEO_PROTECT_VPR_OVERRIDE),
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mc_readl(MC_VIDEO_PROTECT_VPR_OVERRIDE1),
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mc_readl(MC_VIDEO_PROTECT_GPU_OVERRIDE_0),
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mc_readl(MC_VIDEO_PROTECT_GPU_OVERRIDE_1));
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if (fault->flags & E_NO_STATUS) {
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mcerr_pr("MC fault - no status: %s\n", fault->msg);
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return;
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}
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status = __mc_readl(src_chan, fault->stat_reg);
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addr = __mc_readl(src_chan, fault->addr_reg);
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if (fault->flags & E_TWO_STATUS) {
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mcerr_pr("MC fault - %s\n", fault->msg);
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mcerr_pr("status: 0x%08x status2: 0x%08llx\n",
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status, addr);
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return;
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|
|
}
|
||
|
|
|
||
|
|
secure = !!(status & MC_ERR_STATUS_SECURE);
|
||
|
|
write = !!(status & MC_ERR_STATUS_WRITE);
|
||
|
|
client_id = status & 0xff;
|
||
|
|
client = &mc_clients[client_id <= mc_client_last ?
|
||
|
|
client_id : mc_client_last];
|
||
|
|
|
||
|
|
/*
|
||
|
|
* LPAE: make sure we get the extra 2 physical address bits available
|
||
|
|
* and pass them down to the printing function.
|
||
|
|
*/
|
||
|
|
addr |= (((phys_addr_t)(status & MC_ERR_STATUS_ADR_HI)) << 12);
|
||
|
|
|
||
|
|
mcerr_pr("(%d) %s: %s\n", client->swgid, client->name, fault->msg);
|
||
|
|
mcerr_pr(" status = 0x%08x; addr = 0x%08llx\n", status,
|
||
|
|
(long long unsigned int)addr);
|
||
|
|
mcerr_pr(" secure: %s, access-type: %s\n",
|
||
|
|
secure ? "yes" : "no", write ? "write" : "read");
|
||
|
|
}
|
||
|
|
|
||
|
|
static void log_mcerr_fault(unsigned int irq)
|
||
|
|
{
|
||
|
|
int faults_handled = 0;
|
||
|
|
const struct mc_error *err;
|
||
|
|
int mc_channel = MC_BROADCAST_CHANNEL;
|
||
|
|
u32 int_status, ch_int_status, hubc_int_status;
|
||
|
|
u32 g_intstatus = mc_readl(MC_GLOBAL_INTSTATUS);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* If multiple interrupts come in just handle the first one we see. The
|
||
|
|
* HW only keeps track of 1 interrupt's data and we don't know which
|
||
|
|
* particular fault is actually being kept...
|
||
|
|
*/
|
||
|
|
if (g_intstatus & (BIT(INTSTATUS_CH0)) ||
|
||
|
|
g_intstatus & (BIT(INTSTATUS_HUB0))) {
|
||
|
|
mc_channel = 0;
|
||
|
|
} else if (g_intstatus & (BIT(INTSTATUS_CH1)) ||
|
||
|
|
g_intstatus & (BIT(INTSTATUS_HUB1))) {
|
||
|
|
mc_channel = 1;
|
||
|
|
} else if (g_intstatus & (BIT(INTSTATUS_CH2))) {
|
||
|
|
mc_channel = 2;
|
||
|
|
} else if (g_intstatus & (BIT(INTSTATUS_CH3))) {
|
||
|
|
mc_channel = 3;
|
||
|
|
} else if (g_intstatus & (BIT(INTSTATUS_HUBC))) {
|
||
|
|
mc_channel = MC_BROADCAST_CHANNEL;
|
||
|
|
} else {
|
||
|
|
#ifdef CONFIG_TEGRA_MC_TRACE_PRINTK
|
||
|
|
trace_printk("mcerr: unknown source (intstatus = 0x%08x)\n",
|
||
|
|
g_intstatus);
|
||
|
|
#endif
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
int_status = __mc_readl(mc_channel, MC_INTSTATUS);
|
||
|
|
ch_int_status = __mc_readl(mc_channel, MC_CH_INTSTATUS);
|
||
|
|
hubc_int_status = __mc_readl(mc_channel, MC_HUBC_INTSTATUS);
|
||
|
|
|
||
|
|
for (err = hub_mc_errors; err->sig && err->msg; err++) {
|
||
|
|
if ((int_status & mc_int_mask) != err->sig)
|
||
|
|
continue;
|
||
|
|
log_fault(mc_channel, err);
|
||
|
|
__mc_writel(mc_channel, int_status, MC_INTSTATUS);
|
||
|
|
faults_handled++;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (err = ch_mc_errors; err->sig && err->msg; err++) {
|
||
|
|
if ((ch_int_status) != err->sig)
|
||
|
|
continue;
|
||
|
|
log_fault(mc_channel, err);
|
||
|
|
__mc_writel(mc_channel, ch_int_status, MC_CH_INTSTATUS);
|
||
|
|
faults_handled++;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (err = hubc_mc_errors; err->sig && err->msg; err++) {
|
||
|
|
if ((hubc_int_status) != err->sig)
|
||
|
|
continue;
|
||
|
|
log_fault(mc_channel, err);
|
||
|
|
__mc_writel(mc_channel, hubc_int_status, MC_HUBC_INTSTATUS);
|
||
|
|
faults_handled++;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!faults_handled)
|
||
|
|
pr_err("unknown mcerr fault, int_status=0x%08x, "
|
||
|
|
"ch_int_status=0x%08x, hubc_int_status=0x%08x\n",
|
||
|
|
int_status, ch_int_status, hubc_int_status);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct mcerr_ops mcerr_ops = {
|
||
|
|
.nr_clients = ARRAY_SIZE(mc_clients),
|
||
|
|
.intr_descriptions = t186_intr_info,
|
||
|
|
.clear_interrupt = clear_interrupt,
|
||
|
|
.log_mcerr_fault = log_mcerr_fault,
|
||
|
|
.mc_clients = mc_clients,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct mcerr_ops *t18x_mcerr_of_setup(struct device_node *np)
|
||
|
|
{
|
||
|
|
pr_info("mcerr ops are set to t18x\n");
|
||
|
|
return &mcerr_ops;
|
||
|
|
}
|
||
|
|
|
||
|
|
MCERR_OF_DECLARE(mcerr_of, "nvidia,tegra-t18x-mc", t18x_mcerr_of_setup);
|