289 lines
6.3 KiB
C
289 lines
6.3 KiB
C
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/*
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* dev.h
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*
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* A header file for Host driver for ADSP and APE
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*
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* Copyright (C) 2014-2019, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __TEGRA_NVADSP_DEV_H
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#define __TEGRA_NVADSP_DEV_H
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#include <linux/tegra_nvadsp.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <linux/debugfs.h>
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include "hwmailbox.h"
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#include "amc.h"
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/*
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* Note: These enums should be aligned to the regs mentioned in the
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* device tree
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*/
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enum {
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AMC,
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AMISC,
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ABRIDGE,
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UNIT_FPGA_RST,
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AHSP,
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APE_MAX_REG
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};
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enum {
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ADSP_DRAM1,
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ADSP_DRAM2,
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ADSP_MAX_DRAM_MAP
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};
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/*
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* Note: These enums should be aligned to the adsp_mem node mentioned in the
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* device tree
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*/
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enum adsp_mem_dt {
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ADSP_OS_ADDR,
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ADSP_OS_SIZE,
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ADSP_APP_ADDR,
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ADSP_APP_SIZE,
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ARAM_ALIAS_0_ADDR,
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ARAM_ALIAS_0_SIZE,
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ACSR_ADDR, /* ACSR: ADSP CPU SHARED REGION */
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ACSR_SIZE,
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ADSP_MEM_END,
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};
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enum adsp_evp_dt {
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ADSP_EVP_BASE,
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ADSP_EVP_SIZE,
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ADSP_EVP_END,
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};
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enum adsp_unit_fpga_reset {
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ADSP_ASSERT,
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ADSP_DEASSERT,
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ADSP_UNIT_FPGA_RESET_END,
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};
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#define AMISC_REGS 0x2000
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#define AMISC_ADSP_L2_REGFILEBASE 0x10
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#define AMISC_SHRD_SMP_STA 0x14
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#define AMISC_SEM_REG_START 0x1c
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#define AMISC_SEM_REG_END 0x44
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#define AMISC_TSC 0x48
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#define AMISC_ACTMON_AVG_CNT 0x81c
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#define AMISC_REG_START_OFFSET 0x0
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#define AMISC_REG_MBOX_OFFSET 0x64
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#define ADSP_ACTMON_REG_START_OFFSET 0x800
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#define ADSP_ACTMON_REG_END_OFFSET 0x828
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enum nvadsp_virqs {
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MBOX_SEND_VIRQ,
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MBOX_RECV_VIRQ,
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WDT_VIRQ,
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WFI_VIRQ,
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AMC_ERR_VIRQ,
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ACTMON_VIRQ,
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NVADSP_VIRQ_MAX,
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};
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struct nvadsp_pm_state {
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u32 aram[AMC_ARAM_WSIZE];
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uint32_t amc_regs[AMC_REGS];
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uint32_t amisc_regs[AMISC_REGS];
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u32 *evp;
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void *evp_ptr;
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};
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struct nvadsp_hwmb {
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u32 reg_idx;
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u32 hwmbox0_reg;
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u32 hwmbox1_reg;
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u32 hwmbox2_reg;
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u32 hwmbox3_reg;
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u32 hwmbox4_reg;
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u32 hwmbox5_reg;
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u32 hwmbox6_reg;
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u32 hwmbox7_reg;
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};
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typedef int (*reset_init) (struct platform_device *pdev);
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typedef int (*os_init) (struct platform_device *pdev);
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#ifdef CONFIG_PM
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typedef int (*pm_init) (struct platform_device *pdev);
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#endif
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struct nvadsp_chipdata {
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struct nvadsp_hwmb hwmb;
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u32 adsp_state_hwmbox;
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u32 adsp_thread_hwmbox;
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u32 adsp_irq_hwmbox;
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reset_init reset_init;
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os_init os_init;
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#ifdef CONFIG_PM
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pm_init pm_init;
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#endif
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int wdt_irq;
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int start_irq;
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int end_irq;
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};
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struct nvadsp_drv_data {
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void __iomem **base_regs;
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void __iomem **base_regs_saved;
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struct platform_device *pdev;
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struct resource *dram_region[ADSP_MAX_DRAM_MAP];
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struct hwmbox_queue hwmbox_send_queue;
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struct nvadsp_mbox **mboxes;
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unsigned long *mbox_ids;
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spinlock_t mbox_lock;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *adsp_debugfs_root;
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#endif
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struct clk *ape_clk;
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struct clk *apb2ape_clk;
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struct clk *adsp_clk;
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struct clk *aclk_clk;
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struct clk *adsp_cpu_abus_clk;
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struct clk *adsp_neon_clk;
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struct clk *uartape_clk;
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struct clk *ahub_clk;
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unsigned long adsp_freq; /* in KHz*/
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unsigned long adsp_freq_hz; /* in Hz*/
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unsigned long ape_freq; /* in KHz*/
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unsigned long ape_emc_freq; /* in KHz*/
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int (*runtime_suspend)(struct device *dev);
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int (*runtime_resume)(struct device *dev);
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int (*runtime_idle)(struct device *dev);
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int (*assert_adsp)(struct nvadsp_drv_data *drv_data);
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int (*deassert_adsp)(struct nvadsp_drv_data *drv_data);
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struct reset_control *adspall_rst;
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struct nvadsp_pm_state state;
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bool adsp_os_running;
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bool adsp_os_suspended;
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bool adsp_os_secload;
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void *shared_adsp_os_data;
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#ifdef CONFIG_TEGRA_ADSP_DFS
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bool dfs_initialized;
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#endif
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#ifdef CONFIG_TEGRA_ADSP_ACTMON
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bool actmon_initialized;
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#endif
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#ifdef CONFIG_TEGRA_ADSP_CPUSTAT
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bool cpustat_initialized;
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#endif
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#if defined(CONFIG_TEGRA_ADSP_FILEIO)
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bool adspff_init;
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#endif
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#ifdef CONFIG_TEGRA_ADSP_LPTHREAD
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bool lpthread_initialized;
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#endif
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wait_queue_head_t adsp_health_waitq;
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bool adsp_crashed;
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u32 adsp_mem[ADSP_MEM_END];
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bool adsp_unit_fpga;
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u32 unit_fpga_reset[ADSP_UNIT_FPGA_RESET_END];
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int agic_irqs[NVADSP_VIRQ_MAX];
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struct tegra_bwmgr_client *bwmgr;
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u32 evp_base[ADSP_EVP_END];
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const struct nvadsp_chipdata *chip_data;
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};
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#define ADSP_CONFIG 0x04
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#define MAXCLKLATENCY (3 << 29)
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#define UART_BAUD_RATE 9600
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status_t nvadsp_mbox_init(struct platform_device *pdev);
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int nvadsp_setup_amc_interrupts(struct platform_device *pdev);
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void nvadsp_free_amc_interrupts(struct platform_device *pdev);
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#ifdef CONFIG_TEGRA_ADSP_DFS
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void adsp_cpu_set_rate(unsigned long freq);
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int adsp_dfs_core_init(struct platform_device *pdev);
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int adsp_dfs_core_exit(struct platform_device *pdev);
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u32 adsp_to_emc_freq(u32 adspfreq);
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#endif
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#ifdef CONFIG_TEGRA_ADSP_ACTMON
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int ape_actmon_probe(struct platform_device *pdev);
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#endif
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#ifdef CONFIG_TEGRA_ADSP_CPUSTAT
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int adsp_cpustat_init(struct platform_device *pdev);
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int adsp_cpustat_exit(struct platform_device *pdev);
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#endif
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#if defined(CONFIG_TEGRA_ADSP_FILEIO)
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int adspff_init(struct platform_device *pdev);
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void adspff_exit(void);
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#endif
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#ifdef CONFIG_TEGRA_EMC_APE_DFS
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status_t emc_dfs_init(struct platform_device *pdev);
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void emc_dfs_exit(void);
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#endif
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#ifdef CONFIG_PM
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static inline int __init nvadsp_pm_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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if (drv_data->chip_data->pm_init)
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return drv_data->chip_data->pm_init(pdev);
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return -EINVAL;
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}
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#endif
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static inline int __init nvadsp_reset_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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if (drv_data->chip_data->reset_init)
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return drv_data->chip_data->reset_init(pdev);
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return -EINVAL;
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}
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#ifdef CONFIG_TEGRA_ADSP_LPTHREAD
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int adsp_lpthread_init(bool is_adsp_suspended);
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int adsp_lpthread_resume(void);
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int adsp_lpthread_pause(void);
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int adsp_lpthread_uninit(void);
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int adsp_lpthread_get_state(void);
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int adsp_lpthread_entry(struct platform_device *pdev);
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int adsp_lpthread_exit(struct platform_device *pdev);
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int adsp_lpthread_set_suspend(bool is_suspended);
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#endif
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#endif /* __TEGRA_NVADSP_DEV_H */
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