105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
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/*
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* Copyright (C) 2015-2019, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/tegra_nvadsp.h>
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#include <linux/tegra-hsp.h>
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#include <linux/irqchip/tegra-agic.h>
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#include "dev.h"
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#include "os.h"
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static void nvadsp_dbell_handler(void *data)
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{
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struct platform_device *pdev = data;
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struct device *dev = &pdev->dev;
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dev_info(dev, "APE DBELL handler\n");
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}
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/* Function to return the ADMA page number (0 indexed) used by guest */
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static int tegra_adma_query_dma_page(void)
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{
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struct device_node *np = NULL;
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int adma_page = 0, ret = 0, i = 0;
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static const char *compatible[] = {
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"nvidia,tegra210-adma",
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"nvidia,tegra210-adma-hv",
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"nvidia,tegra186-adma",
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"nvidia,tegra194-adma-hv",
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NULL,
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};
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for (i = 0; compatible[i] != NULL; i++) {
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np = of_find_compatible_node(NULL, NULL, compatible[i]);
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if (np == NULL)
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continue;
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/*
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* In DT, "adma-page" property is 1 indexed
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* If property is present, update return value to be 0 indexed
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* If property is absent, return default value as page 0
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*/
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ret = of_property_read_u32(np, "adma-page", &adma_page);
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if (ret == 0)
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adma_page = adma_page - 1;
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break;
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}
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pr_info("%s: adma-page %d\n", __func__, adma_page);
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return adma_page;
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}
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int nvadsp_os_t18x_init(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device_node *node = dev->of_node;
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int ret, adma_ch_page, val = 0;
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if (of_device_is_compatible(node, "nvidia,tegra18x-adsp-hv")) {
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adma_ch_page = tegra_adma_query_dma_page();
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/* Set ADSP to do decompression again */
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val = ADSP_CONFIG_DECOMPRESS_EN << ADSP_CONFIG_DECOMPRESS_SHIFT;
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/* Set ADSP to know its virtualized configuration */
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val = val | (ADSP_CONFIG_VIRT_EN << ADSP_CONFIG_VIRT_SHIFT);
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/* Encode DMA Page Bits with DMA page information */
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val = val | (adma_ch_page << ADSP_CONFIG_DMA_PAGE_SHIFT);
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/* Write to HWMBOX5 */
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hwmbox_writel(val, drv_data->chip_data->hwmb.hwmbox5_reg);
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/* Clear HWMBOX0 for ADSP Guest reset handling */
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hwmbox_writel(0, drv_data->chip_data->hwmb.hwmbox0_reg);
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return 0;
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}
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ret = tegra_hsp_db_add_handler(HSP_MASTER_APE,
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nvadsp_dbell_handler, pdev);
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if (ret) {
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dev_err(dev, "failed to add HSP_MASTER_APE DB handler\n");
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goto end;
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}
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end:
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return ret;
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}
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