518 lines
13 KiB
C
518 lines
13 KiB
C
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/*
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* RAS driver for T194
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*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/of_device.h>
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#include <linux/arm64_ras.h>
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#include <linux/of_irq.h>
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#include <linux/cpuhotplug.h>
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static int fhi_irq[CONFIG_NR_CPUS];
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static u8 is_ras_probe_done;
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static LIST_HEAD(fhi_callback_list);
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static DEFINE_RAW_SPINLOCK(fhi_lock);
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/* saved hotplug state */
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static enum cpuhp_state hp_state;
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static const struct of_device_id arm64_ras_match[] = {
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{
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.name = "arm64_ras",
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.compatible = "arm,armv8.2-ras",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, arm64_ras_match);
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/* Architecturally defined primary error code
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* Used for decoding ERR<x>STATUS:SERR bits
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*/
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static struct ras_error serr_errors[] = {
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{.name = "No error", .error_code = 0x0},
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{.name = "Implementation defined error", .error_code = 0x1},
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{.name = "Data value from non-associative internal memory",
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.error_code = 0x2},
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{.name = "Implementation defined pin", .error_code = 0x3},
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{.name = "Assertion Failure", .error_code = 0x4},
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{.name = "Internal Data Path", .error_code = 0x5},
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{.name = "Data value from associative memory", .error_code = 0x6},
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{.name = "Address/control value(s) from associative memory",
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.error_code = 0x7},
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{.name = "Data value from a TLB", .error_code = 0x8},
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{.name = "Address/control value(s) from a TLB", .error_code = 0x9},
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{.name = "Data value from producer", .error_code = 0xA},
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{.name = "Address/control value(s) from producer", .error_code = 0xB},
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{.name = "Data value from (non-associative) external memory",
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.error_code = 0xC},
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{.name = "Illegal address (software fault)", .error_code = 0xD},
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{.name = "Illegal access (software fault)", .error_code = 0xE},
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{.name = "Illegal state (software fault)", .error_code = 0xF},
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{.name = "Internal data register", .error_code = 0x10},
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{.name = "Internal control register", .error_code = 0x11},
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{.name = "Error response from slave", .error_code = 0x12},
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{.name = "External timeout", .error_code = 0x13},
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{.name = "Internal timeout", .error_code = 0x14},
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{.name = "Deferred error from slave not supported at master",
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.error_code = 0x15},
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};
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/* Read ERR<X>SELR */
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u64 ras_read_errselr(void)
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{
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u64 errselr;
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asm volatile("mrs %0, s3_0_c5_c3_1" : "=r" (errselr));
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return errselr;
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}
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EXPORT_SYMBOL(ras_read_errselr);
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/* For read/write of any ERR<X> register, error record X is selected
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* by writing to ERRSELR_EL1
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* ISB is needed in the end to ensure this write completes before another
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* read/write to this error record comes in.
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*/
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void ras_write_errselr(u64 errx)
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{
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asm volatile("msr s3_0_c5_c3_1, %0" : : "r" (errx));
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isb();
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}
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EXPORT_SYMBOL(ras_write_errselr);
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/* Read ERR<X>STATUS */
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u64 ras_read_error_status(void)
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{
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u64 status;
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asm volatile("mrs %0, s3_0_c5_c4_2" : "=r" (status));
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return status;
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}
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EXPORT_SYMBOL(ras_read_error_status);
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/* Write to ERR<X>STATUS */
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void ras_write_error_status(u64 status)
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{
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asm volatile("msr s3_0_c5_c4_2, %0" : : "r" (status));
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}
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EXPORT_SYMBOL(ras_write_error_status);
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/* Read ERR<X>ADDR */
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static u64 ras_read_error_address(void)
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{
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u64 addr;
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asm volatile("mrs %0, s3_0_c5_c4_3" : "=r" (addr));
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return addr;
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}
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/* Write to ERR<X>ADDR*/
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void ras_write_error_addr(u64 addr)
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{
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asm volatile("msr s3_0_c5_c4_3, %0" : : "r" (addr));
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}
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EXPORT_SYMBOL(ras_write_error_addr);
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/* Read ERR<X>MISC0 */
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static u64 ras_read_error_misc0(void)
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{
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u64 misc0;
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asm volatile("mrs %0, s3_0_c5_c5_0" : "=r" (misc0));
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return misc0;
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}
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/* Write to ERR<X>MISC0*/
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void ras_write_error_misc0(u64 misc0)
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{
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asm volatile("msr s3_0_c5_c5_0, %0" : : "r" (misc0));
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}
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EXPORT_SYMBOL(ras_write_error_misc0);
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/* Read ERR<X>MISC1 */
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static u64 ras_read_error_misc1(void)
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{
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u64 misc1;
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asm volatile("mrs %0, s3_0_c5_c5_1" : "=r" (misc1));
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return misc1;
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}
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/* Write to ERR<X>MISC1*/
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void ras_write_error_misc1(u64 misc1)
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{
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asm volatile("msr s3_0_c5_c5_1, %0" : : "r" (misc1));
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}
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EXPORT_SYMBOL(ras_write_error_misc1);
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/* Read ERR<X>CTLR_EL1*/
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u64 ras_read_error_control(void)
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{
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u64 err_ctl;
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asm volatile("mrs %0, s3_0_c5_c4_1" : "=r" (err_ctl));
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return err_ctl;
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}
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EXPORT_SYMBOL(ras_read_error_control);
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/* Write to ERR<X>CTLR_EL1*/
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void ras_write_error_control(u64 err_ctl)
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{
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asm volatile("msr s3_0_c5_c4_1, %0" : : "r" (err_ctl));
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}
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EXPORT_SYMBOL(ras_write_error_control);
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/* Read ERR<X>PFGCTL_EL1*/
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u64 ras_read_pfg_control(void)
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{
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u64 pfg_ctl;
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asm volatile("mrs %0, s3_0_c15_c1_4" : "=r" (pfg_ctl));
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return pfg_ctl;
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}
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EXPORT_SYMBOL(ras_read_pfg_control);
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/* Write to ERR<X>PFGCTL_EL1*/
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void ras_write_pfg_control(u64 pfg_ctl)
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{
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asm volatile("msr s3_0_c15_c1_4, %0" : : "r" (pfg_ctl));
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}
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EXPORT_SYMBOL(ras_write_pfg_control);
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/* Read ERR<X>PFGCDN_EL1*/
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u64 ras_read_pfg_cdn(void)
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{
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u64 pfg_cdn;
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asm volatile("mrs %0, s3_0_c15_c1_6" : "=r" (pfg_cdn));
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return pfg_cdn;
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}
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EXPORT_SYMBOL(ras_read_pfg_cdn);
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/* Write to ERR<X>PFGCDN_EL1*/
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void ras_write_pfg_cdn(u64 pfg_cdn)
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{
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asm volatile("msr s3_0_c15_c1_6, %0" : : "r" (pfg_cdn));
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}
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EXPORT_SYMBOL(ras_write_pfg_cdn);
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void unregister_fhi_callback(struct ras_fhi_callback *callback)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&fhi_lock, flags);
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list_del(&callback->node);
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raw_spin_unlock_irqrestore(&fhi_lock, flags);
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}
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EXPORT_SYMBOL(unregister_fhi_callback);
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static unsigned int read_pfr0_ras_version(void)
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{
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return PFR0_RAS(read_cpuid(ID_AA64PFR0_EL1));
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}
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static void is_ras_version1(void *ret)
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{
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*(int *)(ret) = (read_pfr0_ras_version() == PFR0_RAS_VERSION_1);
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}
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/* check if RAS is supported on this CPU
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* ret = 0 if not supported
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* = 1 if supported
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*/
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int is_ras_cpu(int cpu)
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{
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int ret;
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smp_call_function_single(cpu, is_ras_version1, &ret, 1);
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return ret;
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}
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EXPORT_SYMBOL(is_ras_cpu);
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int is_this_ras_cpu(void)
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{
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return read_pfr0_ras_version() == PFR0_RAS_VERSION_1;
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}
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EXPORT_SYMBOL(is_this_ras_cpu);
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int is_ras_ready(void)
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{
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return is_ras_probe_done == 1;
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}
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EXPORT_SYMBOL(is_ras_ready);
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void print_error_record(struct error_record *record, u64 status, int errselr)
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{
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struct ras_error *errors;
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u64 misc0, misc1, addr;
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u16 ierr, serr;
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u64 i;
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int found = 0;
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u64 err_status = 0;
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pr_crit("**************************************\n");
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pr_crit("RAS Error in %s, ERRSELR_EL1=%d:\n", record->name, errselr);
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pr_crit("\tStatus = 0x%llx\n", status);
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/* Find the name of IERR */
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ierr = get_error_status_ierr(status);
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errors = record->errors;
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if (errors) {
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for (i = 0; errors[i].name; i++) {
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if (errors[i].error_code == ierr) {
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pr_crit("\tIERR = %s: 0x%x\n",
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errors[i].name, ierr);
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found = 1;
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break;
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}
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}
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if (!found)
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pr_crit("\tUnknown IERR: 0x%x\n", ierr);
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} else {
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pr_crit("\tBank does not have any known IERR errors\n");
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}
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/* Find the name of SERR */
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found = 0;
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serr = get_error_status_serr(status);
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for (i = 0; serr_errors[i].name; i++) {
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if (serr_errors[i].error_code == serr) {
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pr_crit("\tSERR = %s: 0x%x\n", serr_errors[i].name,
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serr);
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found = 1;
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break;
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}
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}
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if (!found)
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pr_crit("\tUnknown SERR: 0x%x\n", serr);
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if (status & ERRi_STATUS_OF) {
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pr_crit("\tOverflow (there may be more errors) - Uncorrectable\n");
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/* Clear the error by writing 1 to ERRi_STATUS:OF */
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err_status |= ERRi_STATUS_OF;
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}
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if (status & ERRi_STATUS_UE) {
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pr_crit("\tUncorrectable (this is fatal)\n");
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/* Clear the error by writing 1 to ERR_STATUS:UE
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* and 11 to ERR_STATUS:UET
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*/
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err_status |= ERRi_STATUS_UE;
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err_status |= ERRi_STATUS_UET;
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}
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if (get_error_status_ce(status)) {
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pr_crit("\tCorrectable Error\n");
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/* Clear the error by writing 1 to ERR_STATUS:CE */
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err_status |= ERRi_STATUS_CE;
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}
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if (status & ERRi_STATUS_MV) {
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misc0 = ras_read_error_misc0();
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misc1 = ras_read_error_misc1();
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pr_crit("\tMISC0 = 0x%llx\n", misc0);
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pr_crit("\tMISC1 = 0x%llx\n", misc1);
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/* write 1 to clear ERR_STATUS:MV */
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err_status |= ERRi_STATUS_MV;
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}
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if (status & ERRi_STATUS_AV) {
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addr = ras_read_error_address();
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pr_crit("\tADDR = 0x%llx\n", addr);
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/* write 1 to clear ERR_STATUS:AV */
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err_status |= ERRi_STATUS_AV;
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}
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/* Write 1 to clear ERR_STATUS:V */
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err_status |= ERRi_STATUS_VALID;
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/* Write to ERR_STATUS to clear the error */
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ras_write_error_status(err_status);
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pr_crit("**************************************\n");
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}
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EXPORT_SYMBOL(print_error_record);
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/* Fault Handling Interrupt or FHI
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* for handling Correctable Errors
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*/
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static irqreturn_t ras_fhi_isr(int irq, void *dev_id)
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{
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unsigned long flags;
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struct ras_fhi_callback *callback;
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/* Iterate through the banks looking for one with an error */
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pr_crit("CPU%d: RAS: FHI %d detected\n", smp_processor_id(), irq);
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raw_spin_lock_irqsave(&fhi_lock, flags);
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list_for_each_entry(callback, &fhi_callback_list, node) {
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callback->fn();
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}
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raw_spin_unlock_irqrestore(&fhi_lock, flags);
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return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ras_fhi_enable(unsigned int cpu)
|
||
|
|
{
|
||
|
|
if (irq_force_affinity(fhi_irq[cpu], cpumask_of(cpu))) {
|
||
|
|
pr_info("%s: Failed to set IRQ %d affinity to CPU%d\n",
|
||
|
|
__func__, fhi_irq[cpu], cpu);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
enable_irq(fhi_irq[cpu]);
|
||
|
|
pr_info("%s: FHI %d enabled on CPU%d\n", __func__, fhi_irq[cpu], cpu);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ras_fhi_disable(unsigned int cpu)
|
||
|
|
{
|
||
|
|
int boot_cpu = 0;
|
||
|
|
|
||
|
|
disable_irq_nosync(fhi_irq[cpu]);
|
||
|
|
if (irq_force_affinity(fhi_irq[cpu], cpumask_of(boot_cpu)))
|
||
|
|
pr_info("%s: Failed to set IRQ %d affinity to boot cpu %d\n",
|
||
|
|
__func__, fhi_irq[cpu], boot_cpu);
|
||
|
|
pr_info("%s: FHI %d disabled\n", __func__, fhi_irq[cpu]);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Register Fault Handling Interrupt or FHI
|
||
|
|
* for Correctable Errors
|
||
|
|
*/
|
||
|
|
static int ras_register_fhi_isr(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
int err = 0, cpu, irq_count;
|
||
|
|
|
||
|
|
irq_count = platform_irq_count(pdev);
|
||
|
|
|
||
|
|
for_each_possible_cpu(cpu) {
|
||
|
|
BUG_ON(cpu >= irq_count);
|
||
|
|
fhi_irq[cpu] = platform_get_irq(pdev, cpu);
|
||
|
|
if (fhi_irq[cpu] <= 0) {
|
||
|
|
dev_err(&pdev->dev, "No IRQ\n");
|
||
|
|
err = -ENOENT;
|
||
|
|
goto isr_err;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
isr_err:
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This is an API for CPU specific FHI callbacks
|
||
|
|
* to be registered with fhi_isr handler
|
||
|
|
*/
|
||
|
|
int register_fhi_callback(struct ras_fhi_callback *callback, void *cookie)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
int err = 0, cpu = 0;
|
||
|
|
|
||
|
|
raw_spin_lock_irqsave(&fhi_lock, flags);
|
||
|
|
list_add(&callback->node, &fhi_callback_list);
|
||
|
|
raw_spin_unlock_irqrestore(&fhi_lock, flags);
|
||
|
|
|
||
|
|
for_each_possible_cpu(cpu) {
|
||
|
|
err = request_irq(fhi_irq[cpu], ras_fhi_isr,
|
||
|
|
IRQ_PER_CPU, "ras-fhi", cookie);
|
||
|
|
if (err) {
|
||
|
|
pr_err("%s: request_irq(%d) failed (%d)\n", __func__,
|
||
|
|
fhi_irq[cpu], err);
|
||
|
|
goto isr_err;
|
||
|
|
}
|
||
|
|
disable_irq(fhi_irq[cpu]);
|
||
|
|
}
|
||
|
|
/* Ensure that any CPU brought online sets up FHI */
|
||
|
|
hp_state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
|
||
|
|
"arm64_ras:online",
|
||
|
|
ras_fhi_enable,
|
||
|
|
ras_fhi_disable);
|
||
|
|
|
||
|
|
if (hp_state < 0)
|
||
|
|
pr_info("%s: unable to register FHI\n", __func__);
|
||
|
|
|
||
|
|
isr_err:
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(register_fhi_callback);
|
||
|
|
|
||
|
|
static int ras_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
const struct of_device_id *match;
|
||
|
|
int err = 0, cpu, probe = 0;
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
|
||
|
|
/* probe only if RAS is supported on either of the online CPUs */
|
||
|
|
for_each_online_cpu(cpu) {
|
||
|
|
if (is_ras_cpu(cpu))
|
||
|
|
probe = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!probe) {
|
||
|
|
dev_info(dev, "None of the CPUs support RAS");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* register FHI for Correctable Errors */
|
||
|
|
match = of_match_device(of_match_ptr(arm64_ras_match),
|
||
|
|
dev);
|
||
|
|
if (!match) {
|
||
|
|
dev_err(dev, "RAS detected, but no device-tree node found,"
|
||
|
|
" Cannot register RAS fault handler interrupt (FHI)");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
err = ras_register_fhi_isr(pdev);
|
||
|
|
if (err < 0) {
|
||
|
|
dev_info(dev, "Failed to register Fault Handling Interrupts"
|
||
|
|
" ISR");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* make sure we have executed everything in the probe
|
||
|
|
* before setting is_ras_probe_done
|
||
|
|
*/
|
||
|
|
smp_mb();
|
||
|
|
is_ras_probe_done = 1;
|
||
|
|
dev_info(dev, "probed");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ras_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
cpuhp_remove_state(hp_state);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver ras_driver = {
|
||
|
|
.probe = ras_probe,
|
||
|
|
.remove = ras_remove,
|
||
|
|
.driver = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.name = "arm64_ras",
|
||
|
|
.of_match_table = of_match_ptr(arm64_ras_match),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init ras_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&ras_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit ras_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&ras_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
arch_initcall(ras_init);
|
||
|
|
module_exit(ras_exit);
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_DESCRIPTION("ARM64 RAS Driver / FHI handler");
|
||
|
|
|