307 lines
8.1 KiB
C
307 lines
8.1 KiB
C
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/*
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* dsi2lvds.c: dsi 2 lvds controller interface.
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*
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/i2c.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include "dc.h"
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#include "dc_priv.h"
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#include "dsi2lvds.h"
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#include "dsi.h"
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static struct tegra_dc_dsi2lvds_data *dsi2lvds;
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enum i2c_transfer_type {
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I2C_WRITE,
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I2C_READ,
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};
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#define DSI2LVDS_TEGRA_I2C_BUS 3
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#define DSI2LVDS_REG_VAL(addr, val) {(addr), (val)}
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static u8 dsi2lvds_config_clk[][2] = {
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DSI2LVDS_REG_VAL(0x0d, 0x00), /* pLL disable */
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DSI2LVDS_REG_VAL(0x0a, 0x00), /* configure PLL */
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DSI2LVDS_REG_VAL(0x0b, 0x00), /* configure PLL */
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DSI2LVDS_REG_VAL(0x0d, 0x01), /* pLL enable */
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};
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static u8 dsi2lvds_config_dsi[][2] = {
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DSI2LVDS_REG_VAL(0x10, 0x80), /* default left right ganged mode */
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DSI2LVDS_REG_VAL(0x12, 0x08), /* channel A clk range */
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DSI2LVDS_REG_VAL(0x13, 0x08), /* channel B clk range */
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};
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static u8 dsi2lvds_config_lvds[][2] = {
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DSI2LVDS_REG_VAL(0x18, 0x7f),
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};
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static u8 dsi2lvds_config_video[][2] = {
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DSI2LVDS_REG_VAL(0x20, 0x40), /* horizontal pixels on dsi channel A */
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DSI2LVDS_REG_VAL(0x21, 0x01),
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DSI2LVDS_REG_VAL(0x22, 0x40), /* horizontal pixels on dsi channel B */
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DSI2LVDS_REG_VAL(0x23, 0x01),
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DSI2LVDS_REG_VAL(0x24, 0xe0), /* vertical pixels on lvds channel A */
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DSI2LVDS_REG_VAL(0x25, 0x01),
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DSI2LVDS_REG_VAL(0x26, 0x00), /* vertical pixels on lvds channel B */
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DSI2LVDS_REG_VAL(0x27, 0x00),
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DSI2LVDS_REG_VAL(0x28, 0x40), /* Pixel clk delay from dsi to */
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DSI2LVDS_REG_VAL(0x29, 0x01), /* lvds channel A */
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DSI2LVDS_REG_VAL(0x2a, 0x10), /* Pixel clk delay from dsi to */
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DSI2LVDS_REG_VAL(0x2b, 0x00), /* lvds channel B */
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DSI2LVDS_REG_VAL(0x2c, 0x40), /* hsync width channel A */
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DSI2LVDS_REG_VAL(0x2d, 0x00),
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DSI2LVDS_REG_VAL(0x2e, 0x40), /* hsync width channel B */
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DSI2LVDS_REG_VAL(0x2f, 0x00),
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DSI2LVDS_REG_VAL(0x30, 0x02), /* vsync width channel A */
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DSI2LVDS_REG_VAL(0x31, 0x00),
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DSI2LVDS_REG_VAL(0x32, 0x00), /* vsync width channel B */
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DSI2LVDS_REG_VAL(0x33, 0x00),
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DSI2LVDS_REG_VAL(0x34, 0x10), /* h back porch channel A */
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DSI2LVDS_REG_VAL(0x35, 0x00), /* h back porch channel B */
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DSI2LVDS_REG_VAL(0x36, 0x21), /* v back porch channel A */
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DSI2LVDS_REG_VAL(0x37, 0x00), /* v back porch channel B */
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DSI2LVDS_REG_VAL(0x38, 0x10), /* h front porch channel A */
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DSI2LVDS_REG_VAL(0x39, 0x00), /* h front porch channel B */
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DSI2LVDS_REG_VAL(0x3a, 0x0a), /* v front porch channel A */
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DSI2LVDS_REG_VAL(0x3b, 0x00), /* v front porch channel B */
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DSI2LVDS_REG_VAL(0x3c, 0x00), /* channel A/B test pattern */
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};
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static u8 dsi2lvds_soft_reset[][2] = {
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DSI2LVDS_REG_VAL(0x09, 0x01),
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};
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static struct i2c_driver tegra_dsi2lvds_i2c_slave_driver = {
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.driver = {
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.name = "dsi2lvds_bridge",
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},
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};
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static struct i2c_client *init_i2c_slave(struct tegra_dc_dsi_data *dsi)
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{
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struct i2c_adapter *adapter;
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struct i2c_client *client;
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struct i2c_board_info p_data = {
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.type = "dsi2lvds_bridge",
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.addr = 0x2D,
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};
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int bus = DSI2LVDS_TEGRA_I2C_BUS;
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int err = 0;
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adapter = i2c_get_adapter(bus);
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if (!adapter) {
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dev_err(&dsi->dc->ndev->dev,
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"dsi2lvds: can't get adpater for bus %d\n", bus);
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err = -EBUSY;
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goto err;
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}
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client = i2c_new_device(adapter, &p_data);
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i2c_put_adapter(adapter);
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if (!client) {
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dev_err(&dsi->dc->ndev->dev,
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"dsi2lvds: can't add i2c slave device\n");
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err = -EBUSY;
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goto err;
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}
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err = i2c_add_driver(&tegra_dsi2lvds_i2c_slave_driver);
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if (err) {
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dev_err(&dsi->dc->ndev->dev,
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"dsi2lvds: can't add i2c slave driver\n");
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goto err_free;
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}
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return client;
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err:
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return ERR_PTR(err);
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err_free:
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i2c_unregister_device(client);
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return ERR_PTR(err);
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}
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static int tegra_dsi2lvds_init(struct tegra_dc_dsi_data *dsi)
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{
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int err = 0;
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if (dsi2lvds) {
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tegra_dsi_set_outdata(dsi, dsi2lvds);
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return err;
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}
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dsi2lvds = devm_kzalloc(&dsi->dc->ndev->dev, sizeof(*dsi2lvds), GFP_KERNEL);
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if (!dsi2lvds)
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return -ENOMEM;
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dsi2lvds->client_i2c = init_i2c_slave(dsi);
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if (IS_ERR_OR_NULL(dsi2lvds->client_i2c)) {
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dev_err(&dsi->dc->ndev->dev,
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"dsi2lvds: i2c slave setup failure\n");
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}
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dsi2lvds->dsi = dsi;
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tegra_dsi_set_outdata(dsi, dsi2lvds);
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mutex_init(&dsi2lvds->lock);
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return err;
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}
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static void tegra_dsi2lvds_destroy(struct tegra_dc_dsi_data *dsi)
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{
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struct tegra_dc_dsi2lvds_data *dsi2lvds = tegra_dsi_get_outdata(dsi);
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if (!dsi2lvds)
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return;
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mutex_lock(&dsi2lvds->lock);
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i2c_del_driver(&tegra_dsi2lvds_i2c_slave_driver);
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i2c_unregister_device(dsi2lvds->client_i2c);
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mutex_unlock(&dsi2lvds->lock);
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mutex_destroy(&dsi2lvds->lock);
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kfree(dsi2lvds);
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}
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static int dsi2lvds_i2c_transfer(struct tegra_dc_dsi2lvds_data *dsi2lvds,
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u8 transfers[][2], u32 no_of_tranfers,
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enum i2c_transfer_type type)
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{
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struct i2c_msg *i2c_msg_transfer;
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struct i2c_client *client = dsi2lvds->client_i2c;
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int err = 0;
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u32 cnt = 0;
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i2c_msg_transfer = kzalloc
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(no_of_tranfers * sizeof(*i2c_msg_transfer), GFP_KERNEL);
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if (!i2c_msg_transfer)
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return -ENOMEM;
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for (cnt = 0; cnt < no_of_tranfers; cnt++) {
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i2c_msg_transfer[cnt].addr = client->addr;
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i2c_msg_transfer[cnt].flags = type;
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i2c_msg_transfer[cnt].len = 2;
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i2c_msg_transfer[cnt].buf = transfers[cnt];
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}
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for (cnt = 0; cnt < no_of_tranfers; cnt++) {
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err = i2c_transfer(client->adapter, &i2c_msg_transfer[cnt], 1);
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if (err < 0) {
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dev_err(&dsi2lvds->dsi->dc->ndev->dev,
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"dsi2lvds: i2c write failed\n");
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break;
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}
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msleep(10);
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}
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kfree(i2c_msg_transfer);
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return err;
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}
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static void tegra_dsi2lvds_enable(struct tegra_dc_dsi_data *dsi)
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{
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struct tegra_dc_dsi2lvds_data *dsi2lvds = tegra_dsi_get_outdata(dsi);
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int err = 0;
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if (dsi2lvds && dsi2lvds->dsi2lvds_enabled)
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return;
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mutex_lock(&dsi2lvds->lock);
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err = dsi2lvds_i2c_transfer(dsi2lvds, dsi2lvds_soft_reset,
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ARRAY_SIZE(dsi2lvds_soft_reset), I2C_WRITE);
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if (err < 0) {
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dev_err(&dsi->dc->ndev->dev, "dsi2lvds: Soft reset failed\n");
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goto fail;
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}
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err = dsi2lvds_i2c_transfer(dsi2lvds, dsi2lvds_config_clk,
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ARRAY_SIZE(dsi2lvds_config_clk), I2C_WRITE);
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if (err < 0) {
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dev_err(&dsi->dc->ndev->dev, "dsi2lvds: Init clk failed\n");
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goto fail;
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}
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if (dsi2lvds->dsi->info.ganged_type ==
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TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
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u32 cnt;
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for (cnt = 0;
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cnt < ARRAY_SIZE(dsi2lvds_config_dsi); cnt++) {
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if (dsi2lvds_config_dsi[cnt][0] == 0x10)
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/* select odd even ganged mode */
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dsi2lvds_config_dsi[cnt][1] &= ~(1 << 7);
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}
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}
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err = dsi2lvds_i2c_transfer(dsi2lvds, dsi2lvds_config_dsi,
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ARRAY_SIZE(dsi2lvds_config_dsi), I2C_WRITE);
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if (err < 0) {
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dev_err(&dsi->dc->ndev->dev, "dsi2lvds: Init dsi failed\n");
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goto fail;
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}
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err = dsi2lvds_i2c_transfer(dsi2lvds, dsi2lvds_config_lvds,
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ARRAY_SIZE(dsi2lvds_config_lvds), I2C_WRITE);
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if (err < 0) {
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dev_err(&dsi->dc->ndev->dev, "dsi2lvds: Init lvds failed\n");
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goto fail;
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}
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err = dsi2lvds_i2c_transfer(dsi2lvds, dsi2lvds_config_video,
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ARRAY_SIZE(dsi2lvds_config_video), I2C_WRITE);
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if (err < 0) {
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dev_err(&dsi->dc->ndev->dev, "dsi2lvds: Init video failed\n");
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goto fail;
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}
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dsi2lvds->dsi2lvds_enabled = true;
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fail:
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mutex_unlock(&dsi2lvds->lock);
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}
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static void tegra_dsi2lvds_disable(struct tegra_dc_dsi_data *dsi)
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{
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/* To be done */
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}
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#ifdef CONFIG_PM
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static void tegra_dsi2lvds_suspend(struct tegra_dc_dsi_data *dsi)
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{
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dsi2lvds->dsi2lvds_enabled = false;
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/* To be done */
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}
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static void tegra_dsi2lvds_resume(struct tegra_dc_dsi_data *dsi)
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{
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/* To be done */
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}
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#endif
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struct tegra_dsi_out_ops tegra_dsi2lvds_ops = {
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.init = tegra_dsi2lvds_init,
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.destroy = tegra_dsi2lvds_destroy,
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.enable = tegra_dsi2lvds_enable,
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.disable = tegra_dsi2lvds_disable,
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#ifdef CONFIG_PM
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.suspend = tegra_dsi2lvds_suspend,
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.resume = tegra_dsi2lvds_resume,
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#endif
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};
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