127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
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/*
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* tc358870.h: HDMI to DSI bridge driver.
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HDMI2DSI_TC358870_
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#define _HDMI2DSI_TC358870_
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#include "panel/board-panel.h"
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#define MAX_BRIDGE_INSTANCES 2
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#define NUMOF_BIT_PER_BYTE 8
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#define REG_LEN 2
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#define MHZ_500 500000000
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#define MHZ_250 250000000
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#define MHZ_125 125000000
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#define MHZ 1000000
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/* DCS */
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#define DATA0_MASK 0x00FF
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#define DATA1_MASK 0xFF00
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#define LONG_PKT_MASK 0x8000
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#ifdef CONFIG_TEGRA_HDMI2DSI_TC358870
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extern struct tegra_hdmi_out_ops tegra_hdmi2dsi_ops;
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#else
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#define tegra_hdmi2dsi_ops (*(struct tegra_hdmi_out_ops *) NULL)
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#endif /* CONFIG_TEGRA_HDMI2DSI_TC358870 */
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enum tc358870_dsi_port {
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DSI_TX_NONE = 0,
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DSI_TX_0,
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DSI_TX_1,
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DSI_TX_BOTH
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};
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enum tc358870_clock_mode {
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DSI_NON_CONT_CLK = 0,
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DSI_CONT_CLK
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};
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enum tc358870_ddc5v_delays {
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DDC5V_DELAY_0MS,
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DDC5V_DELAY_50MS,
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DDC5V_DELAY_100MS,
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DDC5V_DELAY_200MS,
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DDC5V_DELAY_MAX = DDC5V_DELAY_200MS,
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};
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struct panel_out {
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u8 n_data_lanes;
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u8 pixel_format;
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u8 refresh_rate;
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struct tegra_dsi_cmd *dsi_init_cmd;
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u16 n_init_cmd;
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struct tegra_dsi_cmd *dsi_suspend_cmd;
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u16 n_suspend_cmd;
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struct tegra_dsi_cmd *dsi_postvideo_cmd;
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u16 n_postvideo_cmd;
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};
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struct tc358870_platform_data {
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struct regulator *dvdd;
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struct regulator *iovdd;
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int reset_gpio; /* GPIOs Pin K8 */
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int bridge_instance; /* bridge instance */
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int panel_connected; /* panel connected */
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u32 refclk_hz; /* 40 - 50 MHz */
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/* DDC +5V debounce delay */
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enum tc358870_ddc5v_delays ddc5v_delay;
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enum tc358870_dsi_port dsi_port;/* DSI output */
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bool enable_hdcp; /* HDCP not yet implemented */
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/* DSI */
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/* The values in brackets can serve as a starting point. */
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u32 lineinitcnt; /* (0x00000FA0) */
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u32 lptxtimecnt; /* (0x00000004) */
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u32 tclk_headercnt; /* (0x00180203) */
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u32 tclk_trailcnt; /* (0x00040005) */
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u32 ths_headercnt; /* (0x000D0004) */
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u32 twakeup; /* (0x00003E80) */
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u32 tclk_postcnt; /* (0x0000000A) */
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u32 ths_trailcnt; /* (0x00080006) */
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u32 hstxvregcnt; /* (0x00000020) */
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u32 btacnt; /* (0x00000020) */
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/* PLL */
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/* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
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u16 pll_prd; /* PRD from Macro + 1 (0x0A) */
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u16 pll_fbd; /* FBD from Macro + 1 (0x7D) */
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};
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struct tc358870_state {
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struct tc358870_platform_data pdata; /* Bridge structure */
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struct panel_out pout; /* Panel structure */
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struct tegra_hdmi *hdmi;
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struct i2c_client *i2c_client;
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struct tegra_dc_mode *mode;
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struct tegra_panel_ops *out_ops;
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struct dentry *debugdir;
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bool enabled;
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bool power_down;
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struct mutex lock;
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/* edid */
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u8 edid_blocks_written;
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};
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#endif /* _HDMI2DSI_TC358870_ */
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