109 lines
3.6 KiB
C
109 lines
3.6 KiB
C
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/*
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* sn65dsi85_dsi2lvds.h: dsi to lvds sn65dsi85 controller driver.
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*
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* Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Tow Wang <toww@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_SN65DSI85_DSI2LVDS_H
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#define __DRIVERS_VIDEO_TEGRA_DC_SN65DSI85_DSI2LVDS_H
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struct tegra_dc_dsi2lvds_data {
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struct tegra_dc_dsi_data *dsi;
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struct i2c_client *client_i2c;
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struct regmap *regmap;
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bool dsi2lvds_enabled;
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struct mutex lock;
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int en_gpio; /* GPIO */
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int en_gpio_flags;
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int pll_refclk_cfg;
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int dsi_clk_div_mult;
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int dsi_cfg1;
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int dsi_cha_clk_range;
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int dsi_chb_clk_range;
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int lvds_format;
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int video_cha_line_low;
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int video_cha_line_high;
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int video_chb_line_low;
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int video_chb_line_high;
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int cha_vert_disp_size_low;
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int cha_vert_disp_size_high;
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int h_pulse_width_low;
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int h_pulse_width_high;
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int v_pulse_width_low;
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int v_pulse_width_high;
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int h_back_porch;
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int v_back_porch;
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int h_front_porch;
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int v_front_porch;
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int cha_sync_delay_low;
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int cha_sync_delay_high;
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struct dentry *debugdir;
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};
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#define SN65DSI85_DEVICE_ID 0x00
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#define SN65DSI85_SOFT_RESET 0X09
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#define SN65DSI85_PLL_REFCLK_CFG 0x0A
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#define SN65DSI85_DIVIDER_MULTIPLIER 0x0B
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#define SN65DSI85_PLL_EN 0x0D
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#define SN65DSI85_DSI_CFG1 0x10
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#define SN65DSI85_DSI_CFG2 0x11
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#define SN65DSI85_DSI_CHA_CLK_RANGE 0x12
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#define SN65DSI85_DSI_CHB_CLK_RANGE 0x13
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#define SN65DSI85_LVDS_FORMAT 0x18
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#define SN65DSI85_LVDS_VOLTAGE 0x19
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#define SN65DSI85_LVDS_TERMINAL 0x1A
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#define SN65DSI85_LVDS_CM_ADJUST 0x1B
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#define SN65DSI85_VIDEO_CHA_LINE_LOW 0x20
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#define SN65DSI85_VIDEO_CHA_LINE_HIGH 0x21
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#define SN65DSI85_VIDEO_CHB_LINE_LOW 0x22
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#define SN65DSI85_VIDEO_CHB_LINE_HIGH 0x23
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#define SN65DSI85_CHA_VERT_DISP_SIZE_LOW 0x24
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#define SN65DSI85_CHA_VERT_DISP_SIZE_HIGH 0x25
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#define SN65DSI85_CHB_VERT_DISP_SIZE_LOW 0x26
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#define SN65DSI85_CHB_VERT_DISP_SIZE_HIGH 0x27
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#define SN65DSI85_CHA_SYNC_DELAY_LOW 0x28
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#define SN65DSI85_CHA_SYNC_DELAY_HIGH 0x29
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#define SN65DSI85_CHB_SYNC_DELAY_LOW 0x2A
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#define SN65DSI85_CHB_SYNC_DELAY_HIGH 0x2B
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#define SN65DSI85_CHA_HSYNC_PULSE_WIDTH_LOW 0x2C
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#define SN65DSI85_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2D
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#define SN65DSI85_CHB_HSYNC_PULSE_WIDTH_LOW 0x2E
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#define SN65DSI85_CHB_HSYNC_PULSE_WIDTH_HIGH 0x2F
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#define SN65DSI85_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
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#define SN65DSI85_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
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#define SN65DSI85_CHB_VSYNC_PULSE_WIDTH_LOW 0x32
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#define SN65DSI85_CHB_VSYNC_PULSE_WIDTH_HIGH 0x33
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#define SN65DSI85_CHA_HORIZONTAL_BACK_PORCH 0x34
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#define SN65DSI85_CHB_HORIZONTAL_BACK_PORCH 0x35
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#define SN65DSI85_CHA_VERTICAL_BACK_PORCH 0x36
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#define SN65DSI85_CHB_VERTICAL_BACK_PORCH 0x37
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#define SN65DSI85_CHA_HORIZONTAL_FRONT_PORCH 0x38
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#define SN65DSI85_CHB_HORIZONTAL_FRONT_PORCH 0x39
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#define SN65DSI85_CHA_VERTICAL_FRONT_PORCH 0x3A
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#define SN65DSI85_CHB_VERTICAL_FRONT_PORCH 0x3B
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#define SN65DSI85_COLOR_BAR_CFG 0x3C
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#define SN65DSI85_RIGHT_CROP 0x3D
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#define SN65DSI85_LEFT_CROP 0x3E
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#define SN65DSI85_IRQ_EN 0xE0
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#define SN65DSI85_CHA_IRQ_MASK 0xE1
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#define SN65DSI85_CHB_IRQ_MASK 0xE2
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#define SN65DSI85_CHA_IRQ_STATUS 0xE5
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#define SN65DSI85_CHB_IRQ_STATUS 0xE6
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#define RETRYLOOP 2
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#endif
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