323 lines
8.2 KiB
C
323 lines
8.2 KiB
C
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/*
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* tc358767_dsi2edp.h: dsi-edp controller tc358767 driver.
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*
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/i2c.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/swab.h>
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#include <linux/module.h>
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#include "dc.h"
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#include "dc_priv.h"
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#include "tc358767_dsi2edp.h"
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#include "dsi.h"
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static struct tegra_dsi2edp *dsi2edp;
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static struct i2c_client *dsi2edp_i2c_client;
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enum i2c_transfer_type {
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I2C_WRITE,
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I2C_READ,
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};
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static inline void dsi2edp_reg_write(struct tegra_dsi2edp *dsi2edp,
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unsigned int addr,
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unsigned int val)
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{
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BUG_ON(!dsi2edp);
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if (dsi2edp->i2c_shutdown) {
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pr_err("dsi2edp: i2c shutdown\n");
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return;
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}
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/*
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* TC358767 requires register address in big endian
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* and register value in little endian.
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* Regmap currently sends it all in big endian.
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*/
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regmap_write(dsi2edp->regmap, addr, __swab32(val));
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msleep(50);
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}
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static inline void dsi2edp_reg_read(struct tegra_dsi2edp *dsi2edp,
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unsigned int addr,
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unsigned int *val)
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{
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BUG_ON(!dsi2edp);
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if (dsi2edp->i2c_shutdown) {
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pr_err("dsi2edp: i2c shutdown\n");
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return;
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}
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regmap_read(dsi2edp->regmap, addr, val);
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/*
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* TC358767 returns register value in little endian.
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* Covert it to big endian.
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*/
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*val = __swab32(*val);
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}
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static const struct regmap_config dsi2edp_regmap_config = {
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.reg_bits = 16,
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.val_bits = 32,
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.max_register = 0xa00,
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.reg_stride = 4,
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};
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static int dsi2edp_init(struct tegra_dc_dsi_data *dsi)
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{
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int err = 0;
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if (dsi2edp) {
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tegra_dsi_set_outdata(dsi, dsi2edp);
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return err;
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}
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dsi2edp = devm_kzalloc(&dsi->dc->ndev->dev,
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sizeof(*dsi2edp),
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GFP_KERNEL);
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if (!dsi2edp)
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return -ENOMEM;
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dsi2edp->dsi = dsi;
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dsi2edp->client_i2c = dsi2edp_i2c_client;
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dsi2edp->regmap = devm_regmap_init_i2c(dsi2edp_i2c_client,
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&dsi2edp_regmap_config);
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if (IS_ERR(dsi2edp->regmap)) {
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err = PTR_ERR(dsi2edp->regmap);
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dev_err(&dsi->dc->ndev->dev,
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"tc358767_dsi2edp: regmap init failed\n");
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goto fail;
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}
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dsi2edp->mode = &dsi->dc->mode;
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tegra_dsi_set_outdata(dsi, dsi2edp);
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mutex_init(&dsi2edp->lock);
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fail:
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return err;
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}
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static const struct regmap_config dsi2edp_bl_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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};
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static void dsi2edp_enable(struct tegra_dc_dsi_data *dsi)
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{
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struct tegra_dsi2edp *dsi2edp = tegra_dsi_get_outdata(dsi);
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unsigned int val;
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if (dsi2edp && dsi2edp->enabled)
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return;
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mutex_lock(&dsi2edp->lock);
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dsi2edp_reg_write(dsi2edp, DP0_SRC_CTRL, 0x3086);
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dsi2edp_reg_write(dsi2edp, DP1_SRC_CTRL, 0x2);
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dsi2edp_reg_write(dsi2edp, SYS_PLL_PARAM, 0x0101);
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dsi2edp_reg_write(dsi2edp, DP_PHY_CTRL, 0x3000007);
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dsi2edp_reg_write(dsi2edp, DP1_PLL_CTRL, 0x5);
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dsi2edp_reg_write(dsi2edp, DP0_PLL_CTRL, 0x5);
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msleep(70);
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dsi2edp_reg_write(dsi2edp, PXL_PLL_PARAM, 0x22011f);
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dsi2edp_reg_write(dsi2edp, PXL_PLL_CTRL, 0x5);
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msleep(70);
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/* reset main channel 0 and 1*/
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dsi2edp_reg_write(dsi2edp, DP_PHY_CTRL, 0x13001107);
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msleep(100);
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dsi2edp_reg_write(dsi2edp, DP_PHY_CTRL, 0x3000007);
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msleep(100);
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dsi2edp_reg_read(dsi2edp, 0x800, &val);
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if (!(val & (1<<16))) {
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dev_err(&dsi->dc->ndev->dev,
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"TC358767: main link not ready\n");
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}
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x1);
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msleep(100);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG1, 0x1063f);
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msleep(100);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x1);
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msleep(100);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x9);
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msleep(100);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x2);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x9);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x100);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_WDATA0, 0x20a);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x108);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x108);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_WDATA0, 0x1);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x8);
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dsi2edp_reg_write(dsi2edp, DP0_SNK_LTCTRL, 0x21);
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dsi2edp_reg_write(dsi2edp, DP0_LTLOOP_CTRL, 0xf600000d);
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dsi2edp_reg_write(dsi2edp, DP0_SRC_CTRL, 0x3187);
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dsi2edp_reg_write(dsi2edp, DP0_CTRL, 0x1);
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dsi2edp_reg_write(dsi2edp, DP0_SNK_LTCTRL, 0x22);
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dsi2edp_reg_write(dsi2edp, DP0_SRC_CTRL, 0x3287);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x102);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_WDATA0, 0x0);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x8);
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dsi2edp_reg_write(dsi2edp, DP0_SRC_CTRL, 0x1087);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x200);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x409);
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dsi2edp_reg_write(dsi2edp, PPI_TX_RX_TA, 0x040004);
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dsi2edp_reg_write(dsi2edp, PPI_LPTX_TIME_CNT, 0x4);
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dsi2edp_reg_write(dsi2edp, PPI_D0S_CLRSIPOCOUNT, 0x7);
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dsi2edp_reg_write(dsi2edp, PPI_D1S_CLRSIPOCOUNT, 0x7);
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dsi2edp_reg_write(dsi2edp, PPI_D2S_CLRSIPOCOUNT, 0x7);
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dsi2edp_reg_write(dsi2edp, PPI_D3S_CLRSIPOCOUNT, 0x7);
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dsi2edp_reg_write(dsi2edp, PPI_LANE_ENABLE, 0x1f);
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dsi2edp_reg_write(dsi2edp, DSI_LANE_ENABLE, 0x1f);
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dsi2edp_reg_write(dsi2edp, PPI_STARTPPI, 0x1);
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dsi2edp_reg_write(dsi2edp, DSI_STARTDSI, 0x1);
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dsi2edp_reg_write(dsi2edp, VIDEO_PATH0_CTRL, 0x3000101);
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dsi2edp_reg_write(dsi2edp, H_TIMING_CTRL01, 0x500020);
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dsi2edp_reg_write(dsi2edp, H_TIMING_CTRL02, 0x300780);
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dsi2edp_reg_write(dsi2edp, V_TIMING_CTRL01, 0x170005);
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dsi2edp_reg_write(dsi2edp, V_TIMING_CTRL02, 0x30438);
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dsi2edp_reg_write(dsi2edp, VIDEO_FRAME_TIMING_UPLOAD_ENB0, 0x1);
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dsi2edp_reg_write(dsi2edp, DP0_VIDEO_SYNC_DELAY, 0x3e07f0);
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dsi2edp_reg_write(dsi2edp, DP0_TOT_VAL, 0x4570820);
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dsi2edp_reg_write(dsi2edp, DP0_START_VAL, 0x1c0070);
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dsi2edp_reg_write(dsi2edp, DP0_ACTIVE_VAL, 0x4380780);
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dsi2edp_reg_write(dsi2edp, DP0_SYNC_VAL, 0x80058020);
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dsi2edp_reg_write(dsi2edp, DP0_MISC, 0x1f3f0020);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_ADDR, 0x202);
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dsi2edp_reg_write(dsi2edp, DP0_AUX_CFG0, 0x9);
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dsi2edp_reg_write(dsi2edp, VIDEO_MN_GEN0, 0x36);
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dsi2edp_reg_write(dsi2edp, VIDEO_MN_GEN1, 0x2a30);
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dsi2edp_reg_write(dsi2edp, DP0_CTRL, 0x41);
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dsi2edp_reg_write(dsi2edp, DP0_CTRL, 0x43);
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dsi2edp_reg_write(dsi2edp, SYS_CTRL, 0x1);
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msleep(100);
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dsi2edp->enabled = true;
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mutex_unlock(&dsi2edp->lock);
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}
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static void dsi2edp_destroy(struct tegra_dc_dsi_data *dsi)
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{
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/* TODO */
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}
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static void dsi2edp_disable(struct tegra_dc_dsi_data *dsi)
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{
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dsi2edp->enabled = false;
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}
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#ifdef CONFIG_PM
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static void dsi2edp_suspend(struct tegra_dc_dsi_data *dsi)
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{
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/* TODO */
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}
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static void dsi2edp_resume(struct tegra_dc_dsi_data *dsi)
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{
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/* TODO */
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}
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#endif
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struct tegra_dsi_out_ops tegra_dsi2edp_ops = {
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.init = dsi2edp_init,
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.destroy = dsi2edp_destroy,
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.enable = dsi2edp_enable,
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.disable = dsi2edp_disable,
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#ifdef CONFIG_PM
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.suspend = dsi2edp_suspend,
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.resume = dsi2edp_resume,
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#endif
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};
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static int dsi2edp_i2c_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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dsi2edp_i2c_client = client;
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if (dsi2edp)
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dsi2edp->i2c_shutdown = false;
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return 0;
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}
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static int dsi2edp_i2c_remove(struct i2c_client *client)
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{
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dsi2edp_i2c_client = NULL;
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return 0;
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}
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static void dsi2edp_i2c_shutdown(struct i2c_client *client)
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{
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if (dsi2edp)
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dsi2edp->i2c_shutdown = true;
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}
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static const struct i2c_device_id dsi2edp_id_table[] = {
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{"tc358767_dsi2edp", 0},
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{},
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};
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static struct i2c_driver dsi2edp_i2c_drv = {
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.driver = {
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.name = "tc358767_dsi2edp",
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.owner = THIS_MODULE,
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},
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.probe = dsi2edp_i2c_probe,
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.remove = dsi2edp_i2c_remove,
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.shutdown = dsi2edp_i2c_shutdown,
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.id_table = dsi2edp_id_table,
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};
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static int __init dsi2edp_i2c_client_init(void)
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{
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int err = 0;
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err = i2c_add_driver(&dsi2edp_i2c_drv);
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if (err)
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pr_err("tc358767_dsi2edp: Failed to add i2c client driver\n");
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return err;
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}
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static void __exit dsi2edp_i2c_client_exit(void)
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{
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i2c_del_driver(&dsi2edp_i2c_drv);
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}
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subsys_initcall(dsi2edp_i2c_client_init);
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module_exit(dsi2edp_i2c_client_exit);
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MODULE_LICENSE("GPL");
|