412 lines
11 KiB
C
412 lines
11 KiB
C
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/*
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* tc358770_dsi2edp.c: tc358770_dsi2edp.h: dsi-edp controller tc358770 driver.
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*
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/i2c.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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#include <linux/swab.h>
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#include <linux/module.h>
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#include "dc.h"
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#include "dc_priv.h"
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#include "tc358770_dsi2edp.h"
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#include "dsi.h"
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static struct tegra_dc_dsi2edp_data *tc358770_dsi2edp;
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static struct i2c_client *tc358770_i2c_client;
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enum i2c_transfer_type {
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I2C_WRITE,
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I2C_READ,
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};
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/*
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* TC358770 requires register address in big endian
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* and register value in little endian.
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* Regmap currently sends it all in big endian.
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*/
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#define TO_LITTLE_ENDIAN (true)
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static inline void tc358770_reg_write(struct tegra_dc_dsi2edp_data *dsi2edp,
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unsigned int addr, unsigned int val)
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{
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regmap_write(dsi2edp->regmap, addr,
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TO_LITTLE_ENDIAN ? __swab32(val) : val);
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}
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static inline void tc358770_reg_read(struct tegra_dc_dsi2edp_data *dsi2edp,
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unsigned int addr, unsigned int *val)
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{
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regmap_read(dsi2edp->regmap, addr, val);
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*val = TO_LITTLE_ENDIAN ? __swab32(*val) : *val;
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}
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static const struct regmap_config tc358770_regmap_config = {
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.reg_bits = 16,
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.val_bits = 32,
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};
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static int tc358770_dsi2edp_init(struct tegra_dc_dsi_data *dsi)
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{
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int err = 0;
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if (tc358770_dsi2edp) {
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tegra_dsi_set_outdata(dsi, tc358770_dsi2edp);
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return err;
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}
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tc358770_dsi2edp = devm_kzalloc(&dsi->dc->ndev->dev,
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sizeof(*tc358770_dsi2edp),
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GFP_KERNEL);
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if (!tc358770_dsi2edp)
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return -ENOMEM;
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tc358770_dsi2edp->dsi = dsi;
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tc358770_dsi2edp->client_i2c = tc358770_i2c_client;
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tc358770_dsi2edp->regmap = devm_regmap_init_i2c(tc358770_i2c_client,
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&tc358770_regmap_config);
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if (IS_ERR(tc358770_dsi2edp->regmap)) {
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err = PTR_ERR(tc358770_dsi2edp->regmap);
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dev_err(&dsi->dc->ndev->dev,
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"tc358770_dsi2edp: regmap init failed\n");
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goto fail;
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}
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tc358770_dsi2edp->mode = &dsi->dc->mode;
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tegra_dsi_set_outdata(dsi, tc358770_dsi2edp);
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mutex_init(&tc358770_dsi2edp->lock);
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fail:
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return err;
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}
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static void tc358770_dsi2edp_destroy(struct tegra_dc_dsi_data *dsi)
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{
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struct tegra_dc_dsi2edp_data *dsi2edp =
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tegra_dsi_get_outdata(dsi);
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if (!dsi2edp)
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return;
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tc358770_dsi2edp = NULL;
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mutex_destroy(&dsi2edp->lock);
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}
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static void tc358770_dsi2edp_enable(struct tegra_dc_dsi_data *dsi)
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{
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struct tegra_dc_dsi2edp_data *dsi2edp = tegra_dsi_get_outdata(dsi);
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unsigned val;
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unsigned chip_id;
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if (dsi2edp && dsi2edp->dsi2edp_enabled)
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return;
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mutex_lock(&dsi2edp->lock);
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/* Chip ID */
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tc358770_reg_read(dsi2edp, TC358770_CHIP_ID, &chip_id);
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tc358770_reg_write(dsi2edp, TC358770_LINK_TRAINING_CTRL, 0xC0B5);
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tc358770_reg_write(dsi2edp, TC358770_SYSTEM_CLK_PARAM, 0x0105);
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tc358770_reg_write(dsi2edp, TC358770_PHY_CTRL, 0x0F);
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tc358770_reg_write(dsi2edp, TC358770_LINK_CLK_PLL_CTRL, 0x05);
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msleep(70);
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tc358770_reg_write(dsi2edp,
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TC358770_STREAM_CLK_PLL_PARAM, 0x518146);
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tc358770_reg_write(dsi2edp,
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TC358770_STREAM_CLK_PLL_CTRL, 0x05);
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tc358770_reg_write(dsi2edp, TC358770_PHY_CTRL, 0x1F);
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tc358770_reg_write(dsi2edp, TC358770_PHY_CTRL, 0x0F);
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msleep(70);
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/* Check main channel ready */
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tc358770_reg_read(dsi2edp, TC358770_PHY_CTRL, &val);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG1, 0x01063F);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR, 0x01);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0, 0x09);
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msleep(70);
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/* Check aux channel status */
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_STATUS, &val);
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if (val & (0x01 << 1))
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goto timeout;
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_DPCD_RD_DATA0, &val);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR, 0x02);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0, 0x09);
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msleep(70);
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_STATUS, &val);
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_DPCD_RD_DATA0, &val);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR, 0x0100);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_WR_DATA0, 0x040A);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0, 0x0108);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR, 0x0108);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_WR_DATA0, 0x01);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0, 0x08);
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tc358770_reg_write(dsi2edp,
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TC358770_LINK_TRAINING_SINK_CONFIG, 0x21);
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tc358770_reg_write(dsi2edp,
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TC358770_LINK_TRAINING_LOOP_CTRL, 0x7600000D);
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tc358770_reg_write(dsi2edp, TC358770_LINK_TRAINING_CTRL, 0xC1B5);
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tc358770_reg_write(dsi2edp, TC358770_DP_CTRL, 0x41);
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msleep(70);
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tc358770_reg_read(dsi2edp, TC358770_LINK_TRAINING_STATUS, &val);
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tc358770_reg_write(dsi2edp,
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TC358770_LINK_TRAINING_SINK_CONFIG, 0x22);
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tc358770_reg_write(dsi2edp, TC358770_LINK_TRAINING_CTRL, 0xC2B5);
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msleep(70);
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tc358770_reg_read(dsi2edp, TC358770_LINK_TRAINING_STATUS, &val);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR, 0x0102);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_WR_DATA0, 0x00);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0, 0x08);
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tc358770_reg_write(dsi2edp, TC358770_LINK_TRAINING_CTRL, 0x40B5);
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msleep(70);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR , 0x0200);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0 , 0x0409);
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_STATUS, &val);
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_DPCD_RD_DATA0, &val);
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_DPCD_RD_DATA1, &val);
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msleep(100);
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/* ASSR configuration, 770A(reg 0x0500[0] = 1) supports ASSR,
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* need to check the ASSR capability for eDP panel(0x0500[1] = 0).
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*/
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if (chip_id & 0x01) {
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR , 0x000D);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0 , 0x0009);
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tc358770_reg_read(dsi2edp, TC358770_AUX_CHANNEL_STATUS, &val);
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tc358770_reg_read(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_RD_DATA0, &val);
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if (val & 0x01) {
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/* Enable ASSR*/
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_ADDR, 0x010A);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_DPCD_WR_DATA0, 0x01);
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tc358770_reg_write(dsi2edp,
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TC358770_AUX_CHANNEL_CONFIG0, 0x08);
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}
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}
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/* DSI0 setting */
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tc358770_reg_write(dsi2edp, TC358770_DSI0_PPI_TX_RX_TA , 0x000A000C);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_PPI_LPTXTIMECNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_PPI_D0S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_PPI_D1S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_PPI_D2S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_PPI_D3S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_PPI_LANEENABLE , 0x1F);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI0_DSI_LANEENABLE , 0x1F);
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tc358770_reg_write(dsi2edp, TC358770_DSI0_PPI_START , 0x01);
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tc358770_reg_write(dsi2edp, TC358770_DSI0_DSI_START , 0x01);
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/* DSI1 setting */
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tc358770_reg_write(dsi2edp, TC358770_DSI1_PPI_TX_RX_TA , 0x000A000C);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_PPI_LPTXTIMECNT , 0x08);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_PPI_D0S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_PPI_D1S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_PPI_D2S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_PPI_D3S_CLRSIPOCOUNT , 0x8);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_PPI_LANEENABLE , 0x1F);
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tc358770_reg_write(dsi2edp,
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TC358770_DSI1_DSI_LANEENABLE , 0x1F);
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tc358770_reg_write(dsi2edp, TC358770_DSI1_PPI_START , 0x01);
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tc358770_reg_write(dsi2edp, TC358770_DSI1_DSI_START , 0x01);
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/* Combiner logic */
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tc358770_reg_write(dsi2edp, TC358770_CMD_CTRL , 0x1);
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tc358770_reg_write(dsi2edp, TC358770_LR_SIZE , 0x05000500);
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tc358770_reg_write(dsi2edp, TC358770_RM_PXL , 0x00);
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msleep(70);
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/* lcd ctrl frame size */
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tc358770_reg_write(dsi2edp, TC358770_VIDEO_FRAME_CTRL , 0x28A00100);
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val = dsi2edp->mode->h_back_porch << 16 | dsi2edp->mode->h_sync_width;
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tc358770_reg_write(dsi2edp, TC358770_HORIZONTAL_TIME0 , val);
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val = dsi2edp->mode->h_front_porch << 16 | dsi2edp->mode->h_active;
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tc358770_reg_write(dsi2edp, TC358770_HORIZONTAL_TIME1 , val);
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val = dsi2edp->mode->v_back_porch << 16 | dsi2edp->mode->v_sync_width;
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tc358770_reg_write(dsi2edp, TC358770_VERTICAL_TIME0 , val);
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val = dsi2edp->mode->v_front_porch << 16 | dsi2edp->mode->v_active;
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tc358770_reg_write(dsi2edp, TC358770_VERTICAL_TIME1 , val);
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tc358770_reg_write(dsi2edp,
|
||
|
|
TC358770_VIDEO_FRAME_UPDATE_ENABLE , 0x01);
|
||
|
|
msleep(70);
|
||
|
|
|
||
|
|
/* DP main stream attributes */
|
||
|
|
tc358770_reg_write(dsi2edp,
|
||
|
|
TC358770_VIDEO_FRAME_OUTPUT_DELAY , 0x001F0A70);
|
||
|
|
tc358770_reg_write(dsi2edp, TC358770_VIDEO_FRAME_SIZE , 0x066E0AA0);
|
||
|
|
tc358770_reg_write(dsi2edp, TC358770_VIDEO_FRAME_START , 0x002B0070);
|
||
|
|
tc358770_reg_write(dsi2edp,
|
||
|
|
TC358770_VIDEO_FRAME_ACTIVE_REGION_SIZE , 0x06400A00);
|
||
|
|
tc358770_reg_write(dsi2edp,
|
||
|
|
TC358770_VIDEO_FRAME_SYNC_WIDTH , 0x80068020);
|
||
|
|
msleep(70);
|
||
|
|
|
||
|
|
/* DP flow shape & timestamp */
|
||
|
|
tc358770_reg_write(dsi2edp, TC358770_DP_CONFIG , 0x1EBF0020);
|
||
|
|
|
||
|
|
tc358770_reg_write(dsi2edp,
|
||
|
|
TC358770_NVALUE_VIDEO_CLK_REGEN , 0x0465);
|
||
|
|
tc358770_reg_write(dsi2edp, TC358770_DP_CTRL , 0x41);
|
||
|
|
tc358770_reg_write(dsi2edp, TC358770_DP_CTRL , 0x43);
|
||
|
|
|
||
|
|
tc358770_reg_write(dsi2edp, TC358770_SYSTEM_CTRL , 0x01);
|
||
|
|
|
||
|
|
msleep(70);
|
||
|
|
dsi2edp->dsi2edp_enabled = true;
|
||
|
|
|
||
|
|
timeout:
|
||
|
|
mutex_unlock(&dsi2edp->lock);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void tc358770_dsi2edp_disable(struct tegra_dc_dsi_data *dsi)
|
||
|
|
{
|
||
|
|
struct tegra_dc_dsi2edp_data *dsi2edp = tegra_dsi_get_outdata(dsi);
|
||
|
|
|
||
|
|
dsi2edp->dsi2edp_enabled = false;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PM
|
||
|
|
static void tc358770_dsi2edp_suspend(struct tegra_dc_dsi_data *dsi)
|
||
|
|
{
|
||
|
|
/* To be done */
|
||
|
|
}
|
||
|
|
|
||
|
|
static void tc358770_dsi2edp_resume(struct tegra_dc_dsi_data *dsi)
|
||
|
|
{
|
||
|
|
/* To be done */
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
struct tegra_dsi_out_ops tegra_dsi2edp_ops = {
|
||
|
|
.init = tc358770_dsi2edp_init,
|
||
|
|
.destroy = tc358770_dsi2edp_destroy,
|
||
|
|
.enable = tc358770_dsi2edp_enable,
|
||
|
|
.disable = tc358770_dsi2edp_disable,
|
||
|
|
#ifdef CONFIG_PM
|
||
|
|
.suspend = tc358770_dsi2edp_suspend,
|
||
|
|
.resume = tc358770_dsi2edp_resume,
|
||
|
|
#endif
|
||
|
|
};
|
||
|
|
|
||
|
|
static int tc358770_i2c_probe(struct i2c_client *client,
|
||
|
|
const struct i2c_device_id *id)
|
||
|
|
{
|
||
|
|
tc358770_i2c_client = client;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int tc358770_i2c_remove(struct i2c_client *client)
|
||
|
|
{
|
||
|
|
tc358770_i2c_client = NULL;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct i2c_device_id tc358770_id_table[] = {
|
||
|
|
{"tc358770_dsi2edp", 0},
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct i2c_driver tc358770_i2c_drv = {
|
||
|
|
.driver = {
|
||
|
|
.name = "tc358770_dsi2edp",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
},
|
||
|
|
.probe = tc358770_i2c_probe,
|
||
|
|
.remove = tc358770_i2c_remove,
|
||
|
|
.id_table = tc358770_id_table,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init tc358770_i2c_client_init(void)
|
||
|
|
{
|
||
|
|
int err = 0;
|
||
|
|
|
||
|
|
err = i2c_add_driver(&tc358770_i2c_drv);
|
||
|
|
if (err)
|
||
|
|
pr_err("tc358770_dsi2edp: Failed to add i2c client driver\n");
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit tc358770_i2c_client_exit(void)
|
||
|
|
{
|
||
|
|
i2c_del_driver(&tc358770_i2c_drv);
|
||
|
|
}
|
||
|
|
|
||
|
|
subsys_initcall(tc358770_i2c_client_init);
|
||
|
|
module_exit(tc358770_i2c_client_exit);
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL");
|