73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
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/*
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* clock.c: Functions required for internal dc clock utility.
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Copyright (c) 2010-2017, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/err.h>
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#include <linux/types.h>
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include "dc.h"
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#include "dc_reg.h"
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#include "dc_priv.h"
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unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
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{
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unsigned long rate;
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unsigned long div;
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rate = tegra_dc_clk_get_rate(dc);
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if (TEGRA_DC_OUT_DSI == dc->out->type ||
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TEGRA_DC_OUT_FAKE_DSIA == dc->out->type ||
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TEGRA_DC_OUT_FAKE_DSIB == dc->out->type ||
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TEGRA_DC_OUT_FAKE_DSI_GANGED == dc->out->type) {
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div = DIV_ROUND_CLOSEST(rate * 2, pclk);
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if (tegra_dc_is_nvdisplay())
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return rate; /*shift_clk_div is not available*/
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} else { /* round-up for divider for other display types */
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div = DIV_ROUND_UP(rate * 2, pclk);
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}
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if (tegra_dc_is_t21x()) {
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if (dc->out->type == TEGRA_DC_OUT_HDMI)
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return rate;
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}
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if (div < 2)
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return 0;
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return rate * 2 / div;
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}
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void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
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{
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int pclk;
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if (dc->out_ops->setup_clk)
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pclk = dc->out_ops->setup_clk(dc, clk);
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else
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pclk = 0;
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if (tegra_dc_is_nvdisplay())
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tegra_nvdisp_set_compclk(dc);
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WARN_ONCE(!pclk, "pclk is 0\n");
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#ifdef CONFIG_TEGRA_CORE_DVFS
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tegra_dvfs_set_rate(clk, pclk);
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#endif
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}
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