245 lines
8.0 KiB
C
245 lines
8.0 KiB
C
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/*
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* dc_config.h: Declarations for tegra dc config settings.
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*
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* Copyright (c) 2010-2019, NVIDIA CORPORATION, All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_CONFIG_H
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#define __DRIVERS_VIDEO_TEGRA_DC_DC_CONFIG_H
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#include <linux/errno.h>
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#include <uapi/video/tegra_dc_ext.h>
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#include "dc.h"
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#include "dc_priv.h"
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#define WIN_FEATURE_ENTRY_SIZE 5 /* Size of feature entry args */
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#define TEGRA_WIN_SW_FORMAT_MIN 256
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#define TEGRA_WIN_SW_FORMAT_MAX 267
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/* adjust >32 bit shift for an individual 32-bit word */
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#define BIT_FOR_WORD(word, x) ( \
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(x) >= (word) * 32 && \
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(x) < 32 + (word) * 32 \
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? BIT((x) - (word) * 32) : 0)
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#define BITWORD_SW_FORMAT(x) ( \
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(x) >= TEGRA_WIN_SW_FORMAT_MIN && \
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(x) <= TEGRA_WIN_SW_FORMAT_MAX \
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? BIT(x - TEGRA_WIN_SW_FORMAT_MIN) : 0)
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#define BITWORD3(x) BIT_FOR_WORD(3, x)
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#define BITWORD2(x) BIT_FOR_WORD(2, x)
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#define BITWORD1(x) BIT_FOR_WORD(1, x)
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#define BITWORD0(x) BIT_FOR_WORD(0, x)
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#define HIGHBIT(x) BIT_FOR_WORD(1, x)
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/* Define the supported formats. TEGRA_WIN_FMT_WIN_x macros are defined
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* based on T20/T30 formats. */
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#define TEGRA_WIN_FMT_BASE \
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(BIT(TEGRA_DC_EXT_FMT_T_P8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A4R4G4B4) | \
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BIT(TEGRA_DC_EXT_FMT_T_A1R5G5B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_R5G6B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_R5G5B5A1) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8R8G8B8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8) | \
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BIT(TEGRA_DC_EXT_FMT_T_U8_Y8__V8_Y8) | \
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BIT(TEGRA_DC_EXT_FMT_T_U8_Y8__V8_Y8_TRUE) | \
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BIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N420) | \
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BIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N420_TRUE) | \
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BIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N422) | \
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BIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N422_TRUE) | \
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BIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N422R) | \
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BIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N422R_TRUE))
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#define TEGRA_WIN_FMT_T124_LOW TEGRA_WIN_FMT_BASE
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#define TEGRA_WIN_FMT_T124_HIGH \
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(HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N444) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8___V8_N444_TRUE) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8V8_N420) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___V8U8_N420) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8V8_N422) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___V8U8_N422) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8V8_N420_TRUE) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___V8U8_N420_TRUE) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8V8_N422_TRUE) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___V8U8_N422_TRUE) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8V8_N444_TRUE) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___V8U8_N444_TRUE))
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#define TEGRA_WIN_FMT_T210_LOW TEGRA_WIN_FMT_BASE
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#define TEGRA_WIN_FMT_T210_HIGH (TEGRA_WIN_FMT_T124_HIGH | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___U8V8_N444) | \
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HIGHBIT(TEGRA_DC_EXT_FMT_T_Y8___V8U8_N444))
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/* for windows that support compression */
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#define TEGRA_WIN_FMT_COMPRESSION_T210_LOW \
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(BIT(TEGRA_DC_EXT_FMT_T_A8R8G8B8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8))
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#define TEGRA_WIN_FMT_COMPRESSION_T210_HIGH (0)
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/* for windows that can't support planar rotation */
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#define TEGRA_WIN_FMT_ROTATION_T210_LOW TEGRA_WIN_FMT_BASE
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#define TEGRA_WIN_FMT_ROTATION_T210_HIGH (0)
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#define TEGRA_WIN_FMT_WIN_A \
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(BIT(TEGRA_DC_EXT_FMT_T_P8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A4R4G4B4) | \
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BIT(TEGRA_DC_EXT_FMT_T_A1R5G5B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_R5G6B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_R5G5B5A1) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8R8G8B8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8))
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#define TEGRA_WIN_FMT_WIN_B \
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(TEGRA_WIN_FMT_BASE | \
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BIT(TEGRA_DC_EXT_FMT_T_V8_Y8__U8_Y8) | \
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BIT(TEGRA_DC_EXT_FMT_T_V8_Y8__U8_Y8_TRUE))
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#define TEGRA_WIN_FMT_WIN_C \
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(TEGRA_WIN_FMT_BASE | \
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BIT(TEGRA_DC_EXT_FMT_T_V8_Y8__U8_Y8) | \
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BIT(TEGRA_DC_EXT_FMT_T_V8_Y8__U8_Y8_TRUE))
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/* preferred formats do not include 32-bpp formats */
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#define TEGRA_WIN_PREF_FMT_WIN_B \
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(TEGRA_WIN_FMT_WIN_B & \
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~BIT(TEGRA_DC_EXT_FMT_T_A8R8G8B8) & \
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~BIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8))
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#define TEGRA_WIN_FMT_SIMPLE \
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(BIT(TEGRA_DC_EXT_FMT_T_A4R4G4B4) | \
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BIT(TEGRA_DC_EXT_FMT_T_A1R5G5B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_R5G6B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8R8G8B8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8))
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#define TEGRA_WIN_FMT_SIMPLE_T210_LOW \
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(BIT(TEGRA_DC_EXT_FMT_T_A4R4G4B4) | \
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BIT(TEGRA_DC_EXT_FMT_T_A1R5G5B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_R5G6B5) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8R8G8B8) | \
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BIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8))
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#define TEGRA_WIN_FMT_SIMPLE_T210_HIGH (HIGHBIT(TEGRA_DC_EXT_FMT_T_A8B8G8R8))
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/* For each entry, we define the offset to read specific feature. Define the
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* offset for TEGRA_DC_FEATURE_MAXIMUM_SCALE */
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#define H_SCALE_UP 0
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#define V_SCALE_UP 1
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#define H_FILTER_DOWN 2
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#define V_FILTER_DOWN 3
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/* Define the offset for TEGRA_DC_FEATURE_MAXIMUM_SIZE */
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#define MAX_WIDTH 0
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#define MIN_WIDTH 1
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#define MAX_HEIGHT 2
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#define MIN_HEIGHT 3
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#define CHECK_SIZE(val, min, max) ( \
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((val) < (min) || (val) > (max)) ? -EINVAL : 0)
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/* Define the offset for TEGRA_DC_FEATURE_FILTER_TYPE */
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#define V_FILTER 0
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#define H_FILTER 1
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/* Define the offset for TEGRA_DC_FEATURE_INVERT_TYPE */
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#define H_INVERT 0
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#define V_INVERT 1
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#define SCAN_COLUMN 2
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/* Define the offset for TEGRA_DC_FEATURE_LAYOUT_TYPE. */
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#define PITCHED_LAYOUT 0
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#define TILED_LAYOUT 1
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#define BLOCK_LINEAR 2
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/* Define the offset for TEGRA_DC_FEATURE_BLEND_TYPE. */
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#define BLEND_GENERATION 0
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#define INTERLACE 0
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/* Available operations on feature table. */
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enum {
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HAS_SCALE,
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HAS_TILED,
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HAS_V_FILTER,
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HAS_H_FILTER,
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HAS_GEN2_BLEND,
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GET_WIN_FORMATS,
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GET_WIN_SIZE,
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HAS_BLOCKLINEAR,
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HAS_INTERLACE,
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GET_INVERT,
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};
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enum tegra_dc_feature_option {
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TEGRA_DC_FEATURE_FORMATS,
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TEGRA_DC_FEATURE_BLEND_TYPE,
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TEGRA_DC_FEATURE_MAXIMUM_SIZE,
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TEGRA_DC_FEATURE_MAXIMUM_SCALE,
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TEGRA_DC_FEATURE_FILTER_TYPE,
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TEGRA_DC_FEATURE_LAYOUT_TYPE,
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TEGRA_DC_FEATURE_INVERT_TYPE,
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TEGRA_DC_FEATURE_PREFERRED_FORMATS,
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TEGRA_DC_FEATURE_FIELD_TYPE,
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TEGRA_DC_FEATURE_COMPRESSION_FORMATS,
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TEGRA_DC_FEATURE_ROTATION_FORMATS,
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TEGRA_DC_FEATURE_PACKED_ROTATION_MAXIMUM_SIZE,
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TEGRA_DC_FEATURE_PLANAR_ROTATION_MAXIMUM_SIZE,
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};
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struct tegra_dc_feature_entry {
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u32 window_index;
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u32 option;
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u32 arg[WIN_FEATURE_ENTRY_SIZE];
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};
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struct tegra_dc_feature {
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u32 num_entries;
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struct tegra_dc_feature_entry *entries;
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};
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int tegra_dc_get_feature(struct tegra_dc_feature *feature, int win_idx,
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enum tegra_dc_feature_option option);
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int tegra_dc_feature_has_scaling(struct tegra_dc *dc, int win_idx);
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int tegra_dc_feature_has_tiling(struct tegra_dc *dc, int win_idx);
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int tegra_dc_feature_has_blocklinear(struct tegra_dc *dc, int win_idx);
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int tegra_dc_feature_has_interlace(struct tegra_dc *dc, int win_idx);
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int tegra_dc_feature_has_filter(struct tegra_dc *dc, int win_idx, int operation);
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int tegra_dc_feature_is_gen2_blender(struct tegra_dc *dc, int win_idx);
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int tegra_dc_feature_has_scan_column(struct tegra_dc *dc, int win_idx);
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u32 *tegra_dc_parse_feature(struct tegra_dc *dc, int win_idx, int operation);
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void tegra_dc_feature_register(struct tegra_dc *dc);
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static inline bool win_use_v_filter(struct tegra_dc *dc,
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const struct tegra_dc_win *win)
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{
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return tegra_dc_feature_has_filter(dc, win->idx, HAS_V_FILTER) &&
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(win->flags & TEGRA_WIN_FLAG_SCAN_COLUMN ?
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win->w.full != dfixed_const(win->out_h)
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: win->h.full != dfixed_const(win->out_h));
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}
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static inline bool win_use_h_filter(struct tegra_dc *dc,
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const struct tegra_dc_win *win)
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{
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return tegra_dc_feature_has_filter(dc, win->idx, HAS_H_FILTER) &&
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(win->flags & TEGRA_WIN_FLAG_SCAN_COLUMN ?
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win->h.full != dfixed_const(win->out_w)
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: win->w.full != dfixed_const(win->out_w));
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}
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#endif
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