337 lines
9.7 KiB
C
337 lines
9.7 KiB
C
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/*
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* dp_debug.c: dp debug interface.
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*
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* Copyright (c) 2015-2018 NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/export.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/delay.h>
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#include <linux/version.h>
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#include "dc_reg.h"
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#include "dc_priv.h"
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#include "dp.h"
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#include "dp_lt.h"
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#include "sor_regs.h"
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#include "sor.h"
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
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#include <linux/uaccess.h>
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#else
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#include <asm/uaccess.h>
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#endif
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#ifdef CONFIG_DEBUG_FS
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struct tegra_dp_test_settings default_dp_test_settings = {
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DRIVE_CURRENT_L0,
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PRE_EMPHASIS_L0,
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4,
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NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GBPS,
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TEGRA_DC_DP_TRAINING_PATTERN_DISABLE,
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0,
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"rbr",
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"none",
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false,
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false,
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};
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static inline int parse_bitrate_setting(char *bitrate_name,
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struct tegra_dp_test_settings *test_settings)
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{
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u8 bitrate;
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if (!strcmp(bitrate_name, "rbr"))
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bitrate = NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GBPS;
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else if (!strcmp(bitrate_name, "hbr"))
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bitrate = NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GBPS;
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else if (!strcmp(bitrate_name, "hbr2"))
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bitrate = NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GBPS;
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else if (!strcmp(bitrate_name, "hbr3"))
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bitrate = NV_DPCD_MAX_LINK_BANDWIDTH_VAL_8_10_GBPS;
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else
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return -EINVAL;
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test_settings->bitrate = bitrate;
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test_settings->bitrate_name = bitrate_name;
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return 0;
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}
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static inline int parse_patt_setting(char *patt,
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struct tegra_dp_test_settings *test_settings)
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{
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u8 tpg;
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if (!strcmp(patt, "none"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_DISABLE;
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else if (!strcmp(patt, "t1"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_1;
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else if (!strcmp(patt, "t2"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_2;
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else if (!strcmp(patt, "t3"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_3;
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else if (!strcmp(patt, "d102"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_D102;
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else if (!strcmp(patt, "sblerrrate"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_SBLERRRATE;
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else if (!strcmp(patt, "prbs7"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_PRBS7;
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else if (!strcmp(patt, "pltpat") || !strcmp(patt, "pctpat"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_CSTM;
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else if (!strcmp(patt, "hbr2compliance"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_HBR2_COMPLIANCE;
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else if (!strcmp(patt, "cp2520_pat1"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_CP2520_PAT1;
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else if (!strcmp(patt, "cp2520_pat3"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_CP2520_PAT3;
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else if (!strcmp(patt, "t4"))
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tpg = TEGRA_DC_DP_TRAINING_PATTERN_4;
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else
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return -EINVAL;
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test_settings->tpg = tpg;
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test_settings->patt = patt;
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return 0;
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}
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static int parse_test_settings(const char __user *user_buf, size_t count,
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struct tegra_dp_test_settings *test_settings)
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{
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#define IN_RANGE(val, low, high) ((val) >= (low) && (val) <= (high))
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char *buf, *token, *settings[8];
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int i = 0, j = 0;
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u8 u8_val;
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buf = kzalloc(count + 1, GFP_KERNEL);
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if (!buf) {
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pr_err("dp_debug: Not enough memory for buffer\n");
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return -ENOMEM;
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}
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if (copy_from_user(buf, user_buf, count)) {
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pr_err("dp_debug: Copy from user failed\n");
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goto fail;
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}
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while ((token = strsep(&buf, ",\n")) && *token != '\0')
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settings[i++] = token;
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for (; j < i; j++) {
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char *name = strsep(&settings[j], "=");
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char *val = strsep(&settings[j], "=");
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if (!name || !val)
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goto parse_fail;
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if (!strcmp(name, "br")) {
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if (parse_bitrate_setting(val, test_settings))
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goto parse_fail;
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continue;
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}
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if (!strcmp(name, "patt")) {
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if (parse_patt_setting(val, test_settings))
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goto parse_fail;
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continue;
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}
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if (kstrtou8(val, 10, &u8_val))
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goto parse_fail;
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if (!strcmp(name, "sw") && IN_RANGE(u8_val,
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DRIVE_CURRENT_L0, DRIVE_CURRENT_L3))
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test_settings->drive_strength = u8_val;
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else if (!strcmp(name, "pre") && IN_RANGE(u8_val,
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PRE_EMPHASIS_L0, PRE_EMPHASIS_L3))
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test_settings->preemphasis = u8_val;
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else if (!strcmp(name, "lanes") && (u8_val == 1 || u8_val == 2
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|| u8_val == 4))
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test_settings->lanes = u8_val;
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else if (!strcmp(name, "ssc"))
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pr_info("dp_debug: SSC is fixed, ignoring request\n");
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else if (!strcmp(name, "tx_pu_disable"))
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test_settings->disable_tx_pu = u8_val;
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else if (!strcmp(name, "panel"))
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test_settings->panel_type = u8_val;
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else
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goto parse_fail;
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}
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kfree(buf);
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return 0;
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parse_fail:
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pr_err("dp_debug: Invalid arg or value given\n");
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fail:
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kfree(buf);
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return -EINVAL;
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}
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static int test_settings_show(struct seq_file *s, void *unused)
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{
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struct tegra_dc_dp_data *dp = s->private;
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struct tegra_dp_test_settings *test_settings = &dp->test_settings;
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seq_printf(s, "\tDrive strength: %d\n", test_settings->drive_strength);
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seq_printf(s, "\tPreemphasis level: %d\n", test_settings->preemphasis);
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seq_printf(s, "\tLanes: %d\n", test_settings->lanes);
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seq_printf(s, "\tBitrate: %s\n", test_settings->bitrate_name);
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seq_printf(s, "\tTest pattern: %s\n", test_settings->patt);
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seq_printf(s, "\tSSC %sabled\n", test_settings->disable_ssc ?
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"dis" : "en");
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seq_printf(s, "\tTX_PU %sabled\n", test_settings->disable_tx_pu ?
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"dis" : "en");
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seq_printf(s, "\tPanel type : %s\n", test_settings->panel_type ?
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"Internal" : "External");
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return 0;
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}
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static ssize_t test_settings_set(struct file *file, const char __user *buf,
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size_t count, loff_t *off)
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{
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struct seq_file *s = file->private_data;
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struct tegra_dc_dp_data *dp = s->private;
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struct tegra_dc *dc = dp->dc;
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struct tegra_dc_sor_data *sor = dp->sor;
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struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
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struct tegra_dp_test_settings *test_settings = &dp->test_settings;
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int dc_out_type = dc->out->type;
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u32 vs_reg, pe_reg;
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u32 max_tx_pu;
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if (parse_test_settings(buf, count, test_settings))
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return -EINVAL;
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/* Switch DC out type as TEGRA_DC_OUT_FAKE_DP so that SOR will be
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* enabled as if it was interacting with a fake panel.
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*/
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dc->out->type = TEGRA_DC_OUT_FAKE_DP;
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if (!dc->enabled) {
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/* Set default mode to VGA. tegra_dc_enable needs some mode
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* to be set.
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*/
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tegra_dc_set_default_videomode(dc);
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tegra_dc_enable(dc);
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}
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/* detach SOR and precharge lanes */
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tegra_dc_sor_detach(sor);
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tegra_sor_precharge_lanes(sor);
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tegra_dc_io_start(dc);
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/* Set panel type */
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if (test_settings->panel_type)
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tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
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NV_SOR_DP_SPARE_PANEL_MASK,
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NV_SOR_DP_SPARE_PANEL_INTERNAL);
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else
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tegra_sor_write_field(sor, NV_SOR_DP_SPARE(sor->portnum),
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NV_SOR_DP_SPARE_PANEL_MASK,
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NV_SOR_DP_SPARE_PANEL_EXTERNAL);
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/* set lane count and bitrate */
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cfg->lane_count = test_settings->lanes;
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cfg->link_bw = test_settings->bitrate;
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tegra_dp_update_link_config(dp);
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/* set drive strength, preemphasis, and postcursor */
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vs_reg = dp->pdata->lt_data[DP_VS].data[POST_CURSOR2_L0]
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[test_settings->drive_strength][test_settings->preemphasis];
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pe_reg = dp->pdata->lt_data[DP_PE].data[POST_CURSOR2_L0]
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[test_settings->drive_strength][test_settings->preemphasis];
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tegra_sor_writel(sor, NV_SOR_DC(sor->portnum), vs_reg | (vs_reg << 8) |
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(vs_reg << 16) | (vs_reg << 24));
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tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pe_reg | (pe_reg << 8) |
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(pe_reg << 16) | (pe_reg << 24));
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tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum), 0);
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/* set TX_PU */
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if (test_settings->disable_tx_pu) {
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tegra_sor_write_field(sor,
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nv_sor_dp_padctl(sor->portnum),
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NV_SOR_DP_PADCTL_TX_PU_ENABLE |
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NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
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NV_SOR_DP_PADCTL_TX_PU_DISABLE);
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} else {
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max_tx_pu = dp->pdata->lt_data[DP_TX_PU].data[POST_CURSOR2_L0]
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[test_settings->drive_strength][test_settings->preemphasis];
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tegra_sor_write_field(sor, nv_sor_dp_padctl(sor->portnum),
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NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
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(max_tx_pu <<
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NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT |
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NV_SOR_DP_PADCTL_TX_PU_ENABLE));
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}
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/* send training pattern */
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if (test_settings->tpg == TEGRA_DC_DP_TRAINING_PATTERN_CSTM) {
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if (!strcmp(test_settings->patt, "pltpat")) {
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_0, 0x3e0f83e0);
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_1, 0x0f83e0f8);
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_2, 0x0000f83e);
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} else {
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_0, 0xfe0f83e0);
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_1, 0xaccccccc);
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_2, 0x0000aa8a);
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}
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} else {
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_0, 0);
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_1, 0);
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tegra_sor_writel(sor, NV_SOR_DP_LQ_CSTM_2, 0);
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}
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if (test_settings->tpg == TEGRA_DC_DP_TRAINING_PATTERN_HBR2_COMPLIANCE)
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tegra_sor_writel(sor, NV_SOR_DP_TPG_CONFIG, 0x00FC);
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else
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tegra_sor_writel(sor, NV_SOR_DP_TPG_CONFIG, 0);
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if (test_settings->tpg == TEGRA_DC_DP_TRAINING_PATTERN_CP2520_PAT1 ||
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test_settings->tpg == TEGRA_DC_DP_TRAINING_PATTERN_CP2520_PAT3 ||
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test_settings->tpg == TEGRA_DC_DP_TRAINING_PATTERN_4)
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tegra_dp_set_enhanced_framing(dp, false);
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else
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tegra_dp_set_enhanced_framing(dp, cfg->enhanced_framing);
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tegra_sor_tpg(sor, test_settings->tpg, test_settings->lanes);
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/* restore DC out type */
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dc->out->type = dc_out_type;
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tegra_dc_io_end(dc);
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return count;
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}
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static int test_settings_open(struct inode *inode, struct file *file)
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{
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return single_open(file, test_settings_show, inode->i_private);
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}
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const struct file_operations test_settings_fops = {
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.open = test_settings_open,
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|
|
.read = seq_read,
|
||
|
|
.write = test_settings_set,
|
||
|
|
.llseek = seq_lseek,
|
||
|
|
.release = single_release,
|
||
|
|
};
|
||
|
|
EXPORT_SYMBOL(test_settings_fops);
|
||
|
|
|
||
|
|
#endif
|