109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
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/*
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* drivers/video/tegra/dc/dp_t19x.c
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*
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* Copyright (c) 2017, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "dc.h"
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#include "dp.h"
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#include "dp_lt.h"
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#include "dp_t19x.h"
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#include "sor.h"
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#include "sor_t19x.h"
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int tegra_dp_init_max_link_cfg_t19x(struct tegra_dc_dp_data *dp,
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struct tegra_dc_dp_link_config *cfg)
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{
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u8 dpcd_data = 0;
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int ret = 0;
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cfg->max_lane_count = tegra_dc_dp_get_max_lane_count(dp, &dpcd_data);
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if (cfg->max_lane_count == 0) {
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dev_err(&dp->dc->ndev->dev,
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"dp: Invalid max lane count: %u\n", cfg->max_lane_count);
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return -EINVAL;
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}
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if (dpcd_data & NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES)
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cfg->tps = TEGRA_DC_DP_TRAINING_PATTERN_3;
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else
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cfg->tps = TEGRA_DC_DP_TRAINING_PATTERN_2;
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cfg->support_enhanced_framing =
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(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
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true : false;
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if (dp->sink_cap_valid) {
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dpcd_data = dp->sink_cap[NV_DPCD_MAX_DOWNSPREAD];
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} else {
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ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
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&dpcd_data);
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if (ret)
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return ret;
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}
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/*
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* The check for TPS4 should be after the check for TPS3. That helps
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* assign a higher priority to TPS4
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*/
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if (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_TPS4_SUPPORTED_YES)
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cfg->tps = TEGRA_DC_DP_TRAINING_PATTERN_4;
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cfg->downspread =
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(dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
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true : false;
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cfg->support_fast_lt = (dpcd_data &
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NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ?
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true : false;
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ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL,
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&dpcd_data);
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if (ret)
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return ret;
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cfg->aux_rd_interval = dpcd_data &
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NV_DPCD_TRAINING_AUX_RD_INTERVAL_MASK;
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cfg->max_link_bw = tegra_dc_dp_get_max_link_bw(dp);
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if (cfg->max_link_bw == 0) {
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dev_err(&dp->dc->ndev->dev,
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"dp: Invalid max link bw: %u\n", cfg->max_link_bw);
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return -EINVAL;
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}
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tegra_dp_set_max_link_bw(dp->sor, cfg);
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ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP, &dpcd_data);
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if (ret)
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return ret;
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cfg->alt_scramber_reset_cap =
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(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
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true : false;
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cfg->only_enhanced_framing = (dpcd_data &
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NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
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true : false;
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cfg->edp_cap = (dpcd_data &
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NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ?
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true : false;
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ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_FEATURE_ENUM_LIST, &dpcd_data);
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if (ret)
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return ret;
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cfg->support_vsc_ext_colorimetry = (dpcd_data &
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NV_DPCD_FEATURE_ENUM_LIST_VSC_EXT_COLORIMETRY) ?
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true : false;
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return 0;
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}
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