78 lines
3.1 KiB
C
78 lines
3.1 KiB
C
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/*
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* dpaux.h: dpaux headers.
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION, All rights reserved.
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* Author: Animesh Kishore <ankishore@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVER_VIDEO_TEGRA_DC_DPAUX_H__
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#define __DRIVER_VIDEO_TEGRA_DC_DPAUX_H__
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#define DP_AUX_MAX_BYTES 16
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#define DP_AUX_TIMEOUT_MS 1000
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#define DP_AUX_DEFER_MAX_TRIES 7
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#define DP_AUX_TIMEOUT_MAX_TRIES 3
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#define DP_DPCP_RETRY_SLEEP_US 400
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struct tegra_dc_dpaux_data {
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struct tegra_dc *dc;
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void __iomem *base;
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struct clk *clk;
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struct reset_control *rst;
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struct tegra_prod *prod_list;
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struct device_node *np; /* dpaux@******** */
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atomic_t enable_count;
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struct mutex lock;
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int ctrl_num; /* this should match with sor->ctrl_num */
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int powergate_id;
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};
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enum tegra_dpaux_pad_mode {
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TEGRA_DPAUX_PAD_MODE_AUX = 0,
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TEGRA_DPAUX_PAD_MODE_I2C = 1,
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};
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int tegra_dpaux_readl(struct tegra_dc_dpaux_data *dpaux, u32 reg);
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void tegra_dpaux_writel(struct tegra_dc_dpaux_data *dpaux, u32 reg, u32 val);
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void tegra_dpaux_write_field(struct tegra_dc_dpaux_data *dpaux, u32 reg,
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u32 mask, u32 val);
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void tegra_dpaux_get(struct tegra_dc_dpaux_data *dpaux);
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void tegra_dpaux_put(struct tegra_dc_dpaux_data *dpaux);
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int tegra_dpaux_clk_en(struct tegra_dc_dpaux_data *dpaux);
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void tegra_dpaux_clk_dis(struct tegra_dc_dpaux_data *dpaux);
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void tegra_dpaux_int_toggle(struct tegra_dc_dpaux_data *dpaux, u32 intr,
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bool enable);
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void tegra_dpaux_pad_power(struct tegra_dc_dpaux_data *dpaux, bool on);
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void tegra_dpaux_config_pad_mode(struct tegra_dc_dpaux_data *dpaux,
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enum tegra_dpaux_pad_mode mode);
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void tegra_dpaux_prod_set(struct tegra_dc_dpaux_data *dpaux);
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struct tegra_dc_dpaux_data *tegra_dpaux_init_data(struct tegra_dc *dc,
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struct device_node *sor_np);
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void tegra_dpaux_destroy_data(struct tegra_dc_dpaux_data *dpaux);
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int tegra_dpaux_get_irq(struct tegra_dc_dpaux_data *dpaux);
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int tegra_dc_dpaux_read_chunk_locked(struct tegra_dc_dpaux_data *dpaux,
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u32 cmd, u32 addr, u8 *data, u32 *size, u32 *aux_stat);
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int tegra_dc_dpaux_write_chunk_locked(struct tegra_dc_dpaux_data *dpaux,
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u32 cmd, u32 addr, u8 *data, u32 *size, u32 *aux_stat);
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int tegra_dc_dpaux_read(struct tegra_dc_dpaux_data *dpaux, u32 cmd, u32 addr,
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u8 *data, u32 *size, u32 *aux_stat);
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int tegra_dc_dpaux_write(struct tegra_dc_dpaux_data *dpaux, u32 cmd, u32 addr,
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u8 *data, u32 *size, u32 *aux_stat);
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int tegra_dc_dpaux_i2c_read(struct tegra_dc_dpaux_data *dpaux, u32 i2c_addr,
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u8 *data, u32 *size, u32 *aux_stat);
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int tegra_dc_dpaux_i2c_write(struct tegra_dc_dpaux_data *dpaux, u32 cmd,
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u32 i2c_addr, u8 *data, u32 *size, u32 *aux_stat);
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struct clk *tegra_dpaux_get_clk(struct tegra_dc_dpaux_data *dpaux,
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const char *clk_name);
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#endif
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