1270 lines
60 KiB
C
1270 lines
60 KiB
C
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/*
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* sor_regs.h: sor register definitions.
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*
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* Copyright (c) 2011-2018, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_H__
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#define __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_H__
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#define NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(x) ((x) & 0xff)
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#define NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
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#define NV_SOR_HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x1f) << 16)
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#define NV_SOR_HDMI_BRICK_MUL(x) (((x) >> 2) & 0x1f)
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#define NV_SOR_HDMI_BRICK_DIV 10
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#define NV_SOR_SUPER_STATE0 (0x1)
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#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT (0)
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#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK (0x1)
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#define NV_SOR_SUPER_STATE1 (0x2)
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#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT (3)
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#define NV_SOR_SUPER_STATE1_ATTACHED_NO (0 << 3)
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#define NV_SOR_SUPER_STATE1_ATTACHED_YES (1 << 3)
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#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT (2)
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#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2)
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#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2)
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#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT (0)
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#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK (0x3)
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#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP (0)
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#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE (1)
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#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE (2)
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#define NV_SOR_STATE0 (0x3)
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#define NV_SOR_STATE0_UPDATE_SHIFT (0)
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#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK (0x1)
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#define NV_SOR_STATE0_UPDATE_UPDATE (0x1)
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#define NV_SOR_STATE1 (0x4)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT (17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULTVAL (0 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17)
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#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17)
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#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT (15)
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#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK (0x3 << 15)
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#define NV_SOR_STATE1_ASY_REPLICATE_OFF (0 << 15)
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#define NV_SOR_STATE1_ASY_REPLICATE_X2 (1 << 15)
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#define NV_SOR_STATE1_ASY_REPLICATE_X4 (2 << 15)
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#define NV_SOR_STATE1_ASY_DEPOL_SHIFT (14)
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#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK (0x1 << 14)
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#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14)
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#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14)
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#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT (13)
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#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK (0x1 << 13)
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#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13)
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#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13)
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#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT (12)
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#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK (0x1 << 12)
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#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12)
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#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12)
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#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT (8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_SINGLE_TMDS_B (2 << 8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A (8 << 8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B (9 << 8)
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#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM (15 << 8)
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#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT (6)
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#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK (0x3 << 6)
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#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6)
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#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6)
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#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6)
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#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT (4)
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#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK (0x3 << 4)
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#define NV_SOR_STATE1_ASY_SUBOWNER_NONE (0 << 4)
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#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
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#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
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#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH (3 << 4)
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#define NV_SOR_STATE1_ASY_OWNER_SHIFT (0)
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#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK (0xf)
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#define NV_SOR_STATE1_ASY_OWNER_NONE (0)
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#define NV_SOR_STATE1_ASY_OWNER_HEAD0 (1)
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#define NV_SOR_STATE1_ASY_OWNER_HEAD1 (2)
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#define NV_SOR_STATE1_ASY_OWNER_HEAD2 (3)
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#define NV_SOR_HEADNUM(i) (i+1)
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/* Specific to T18X */
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#define NV_HEAD_STATE0_T18X(i) (0x151 + i)
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#define NV_HEAD_STATE1_T18X(i) (0x154 + i)
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#define NV_HEAD_STATE2_T18X(i) (0x157 + i)
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#define NV_HEAD_STATE3_T18X(i) (0x15a + i)
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#define NV_HEAD_STATE4_T18X(i) (0x15d + i)
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#define NV_HEAD_STATE5_T18X(i) (0x160 + i)
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/* Specific to T21X */
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#define NV_HEAD_STATE0(i) (0x5 + i)
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#define NV_HEAD_STATE1(i) (0x7 + i)
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#define NV_HEAD_STATE2(i) (0x9 + i)
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#define NV_HEAD_STATE3(i) (0xb + i)
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#define NV_HEAD_STATE4(i) (0xd + i)
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#define NV_HEAD_STATE5(i) (0xf + i)
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#define NV_HEAD_STATE0_INTERLACED_SHIFT (4)
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#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (0x3 << 4)
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#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4)
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#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4)
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#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT (3)
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#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (0x1 << 3)
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#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3)
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#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3)
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#define NV_HEAD_STATE0_DYNRANGE_SHIFT (2)
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#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (0x1 << 2)
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#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2)
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#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2)
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#define NV_HEAD_STATE0_COLORSPACE_SHIFT (0)
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#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK (0x3)
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#define NV_HEAD_STATE0_COLORSPACE_RGB (0)
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#define NV_HEAD_STATE0_COLORSPACE_YUV_601 (1)
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#define NV_HEAD_STATE0_COLORSPACE_YUV_709 (2)
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#define NV_HEAD_STATE1_VTOTAL_SHIFT (16)
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#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16)
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#define NV_HEAD_STATE1_HTOTAL_SHIFT (0)
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#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK (0x7fff)
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#define NV_HEAD_STATE2_VSYNC_END_SHIFT (16)
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#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16)
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#define NV_HEAD_STATE2_HSYNC_END_SHIFT (0)
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#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK (0x7fff)
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#define NV_HEAD_STATE3_VBLANK_END_SHIFT (16)
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#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16)
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#define NV_HEAD_STATE3_HBLANK_END_SHIFT (0)
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#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK (0x7fff)
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#define NV_HEAD_STATE4_VBLANK_START_SHIFT (16)
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#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16)
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#define NV_HEAD_STATE4_HBLANK_START_SHIFT (0)
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#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK (0x7fff)
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#define NV_HEAD_STATE5_VBLANK_END_2_SHIFT (16)
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#define NV_HEAD_STATE5_VBLANK_END_2_DEFAULT_MASK (0x7fff << 16)
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#define NV_HEAD_STATE5_HBLANK_END_2_SHIFT (0)
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#define NV_HEAD_STATE5_HBLANK_END_2_DEFAULT_MASK (0x7fff)
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#define NV_SOR_CRC_CNTRL (0x11)
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#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT (0)
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#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DEFAULT_MASK (0x1)
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#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO (0)
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#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES (1)
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#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS (0)
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#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN (1)
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#define NV_SOR_CLK_CNTRL (0x13)
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#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT (0)
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#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK (0x3)
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#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0)
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#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1)
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#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2)
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#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT (2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4 (20 << 2)
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/* Specific to Nvdisplay */
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_16 (8 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_43 (9 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G3_24 (12 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G4_32 (16 << 2)
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#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G8_1 (30 << 2)
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/* Nvdisplay specific registers end here */
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#define NV_SOR_CAP (0x14)
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#define NV_SOR_CAP_DP_A_SHIFT (24)
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#define NV_SOR_CAP_DP_A_DEFAULT_MASK (0x1 << 24)
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#define NV_SOR_CAP_DP_A_FALSE (0 << 24)
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#define NV_SOR_CAP_DP_A_TRUE (1 << 24)
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#define NV_SOR_CAP_DP_B_SHIFT (25)
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#define NV_SOR_CAP_DP_B_DEFAULT_MASK (0x1 << 24)
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#define NV_SOR_CAP_DP_B_FALSE (0 << 24)
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#define NV_SOR_CAP_DP_B_TRUE (1 << 24)
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#define NV_SOR_PWR (0x15)
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#define NV_SOR_PWR_SETTING_NEW_SHIFT (31)
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#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK (0x1 << 31)
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#define NV_SOR_PWR_SETTING_NEW_DONE (0 << 31)
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#define NV_SOR_PWR_SETTING_NEW_PENDING (1 << 31)
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#define NV_SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
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#define NV_SOR_PWR_MODE_SHIFT (28)
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#define NV_SOR_PWR_MODE_DEFAULT_MASK (0x1 << 28)
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#define NV_SOR_PWR_MODE_NORMAL (0 << 28)
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#define NV_SOR_PWR_MODE_SAFE (1 << 28)
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#define NV_SOR_PWR_HALT_DELAY_SHIFT (24)
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#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK (0x1 << 24)
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#define NV_SOR_PWR_HALT_DELAY_DONE (0 << 24)
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#define NV_SOR_PWR_HALT_DELAY_ACTIVE (1 << 24)
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#define NV_SOR_PWR_SAFE_START_SHIFT (17)
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#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK (0x1 << 17)
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#define NV_SOR_PWR_SAFE_START_NORMAL (0 << 17)
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#define NV_SOR_PWR_SAFE_START_ALT (1 << 17)
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#define NV_SOR_PWR_SAFE_STATE_SHIFT (16)
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#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK (0x1 << 16)
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#define NV_SOR_PWR_SAFE_STATE_PD (0 << 16)
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#define NV_SOR_PWR_SAFE_STATE_PU (1 << 16)
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#define NV_SOR_PWR_NORMAL_START_SHIFT (1)
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#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK (0x1 << 1)
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#define NV_SOR_PWR_NORMAL_START_NORMAL (0 << 16)
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#define NV_SOR_PWR_NORMAL_START_ALT (1 << 16)
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#define NV_SOR_PWR_NORMAL_STATE_SHIFT (0)
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#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK (0x1)
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#define NV_SOR_PWR_NORMAL_STATE_PD (0)
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#define NV_SOR_PWR_NORMAL_STATE_PU (1)
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#define NV_SOR_TEST (0x16)
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#define NV_SOR_TEST_TESTMUX_SHIFT (24)
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#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK (0xff << 24)
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#define NV_SOR_TEST_TESTMUX_AVSS (0 << 24)
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#define NV_SOR_TEST_TESTMUX_CLOCKIN (2 << 24)
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#define NV_SOR_TEST_TESTMUX_PLL_VOL (4 << 24)
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#define NV_SOR_TEST_TESTMUX_SLOWCLKINT (8 << 24)
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#define NV_SOR_TEST_TESTMUX_AVDD (16 << 24)
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#define NV_SOR_TEST_TESTMUX_VDDREG (32 << 24)
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#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG (64 << 24)
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#define NV_SOR_TEST_TESTMUX_REGREF_AVDD (128 << 24)
|
||
|
|
#define NV_SOR_TEST_CRC_SHIFT (23)
|
||
|
|
#define NV_SOR_TEST_CRC_DEFAULT_MASK (1 << 23)
|
||
|
|
#define NV_SOR_TEST_CRC_PRE_SERIALIZE (0 << 23)
|
||
|
|
#define NV_SOR_TEST_CRC_POST_DESERIALIZE (1 << 23)
|
||
|
|
#define NV_SOR_TEST_TPAT_SHIFT (20)
|
||
|
|
#define NV_SOR_TEST_TPAT_DEFAULT_MASK (0x7 << 20)
|
||
|
|
#define NV_SOR_TEST_TPAT_LO (0 << 20)
|
||
|
|
#define NV_SOR_TEST_TPAT_TDAT (1 << 20)
|
||
|
|
#define NV_SOR_TEST_TPAT_RAMP (2 << 20)
|
||
|
|
#define NV_SOR_TEST_TPAT_WALK (3 << 20)
|
||
|
|
#define NV_SOR_TEST_TPAT_MAXSTEP (4 << 20)
|
||
|
|
#define NV_SOR_TEST_TPAT_MINSTEP (5 << 20)
|
||
|
|
#define NV_SOR_TEST_DSRC_SHIFT (16)
|
||
|
|
#define NV_SOR_TEST_DSRC_DEFAULT_MASK (0x3 << 16)
|
||
|
|
#define NV_SOR_TEST_DSRC_NORMAL (0 << 16)
|
||
|
|
#define NV_SOR_TEST_DSRC_DEBUG (1 << 16)
|
||
|
|
#define NV_SOR_TEST_DSRC_TGEN (2 << 16)
|
||
|
|
#define NV_SOR_TEST_HEAD_NUMBER_SHIFT (12)
|
||
|
|
#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK (0x3 << 12)
|
||
|
|
#define NV_SOR_TEST_HEAD_NUMBER_NONE (0 << 12)
|
||
|
|
#define NV_SOR_TEST_HEAD_NUMBER_HEAD0 (1 << 12)
|
||
|
|
#define NV_SOR_TEST_HEAD_NUMBER_HEAD1 (2 << 12)
|
||
|
|
#define NV_SOR_TEST_HEAD_NUMBER_HEAD2 (3 << 12)
|
||
|
|
#define NV_SOR_TEST_ATTACHED_SHIFT (10)
|
||
|
|
#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK (0x1 << 10)
|
||
|
|
#define NV_SOR_TEST_ATTACHED_FALSE (0 << 10)
|
||
|
|
#define NV_SOR_TEST_ATTACHED_TRUE (1 << 10)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT (8)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (0x3 << 8)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK (7)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK_MASK (0x1 << 7)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK_ENABLE (1 << 7)
|
||
|
|
#define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK_DISABLE (0 << 7)
|
||
|
|
#define NV_SOR_TEST_INVD_SHIFT (6)
|
||
|
|
#define NV_SOR_TEST_INVD_DISABLE (0 << 6)
|
||
|
|
#define NV_SOR_TEST_INVD_ENABLE (1 << 6)
|
||
|
|
#define NV_SOR_TEST_TEST_ENABLE_SHIFT (1)
|
||
|
|
#define NV_SOR_TEST_TEST_ENABLE_DISABLE (0 << 1)
|
||
|
|
#define NV_SOR_TEST_TEST_ENABLE_ENABLE (1 << 1)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL0_T18X (0x163)
|
||
|
|
#define NV_SOR_PLL1_T18X (0x164)
|
||
|
|
#define NV_SOR_PLL2_T18X (0x165)
|
||
|
|
#define NV_SOR_PLL3_T18X (0x166)
|
||
|
|
#define NV_SOR_PLL4_T18X (0x167)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL0 (0x17)
|
||
|
|
#define NV_SOR_PLL1 (0x18)
|
||
|
|
#define NV_SOR_PLL2 (0x19)
|
||
|
|
#define NV_SOR_PLL3 (0x1a)
|
||
|
|
#define NV_SOR_PLL4 (-1)
|
||
|
|
#define NV_SOR_PLL5 (-1)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL0_ICHPMP_SHFIT (24)
|
||
|
|
#define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK (0xf << 24)
|
||
|
|
#define NV_SOR_PLL0_FILTER_SHIFT (16)
|
||
|
|
#define NV_SOR_PLL0_FILTER_DEFAULT_MASK (0xf << 16)
|
||
|
|
#define NV_SOR_PLL0_TXREG_LEVEL_SHIFT (12)
|
||
|
|
#define NV_SOR_PLL0_TXREG_LEVEL_DEFAULT_MASK (0x3 << 12)
|
||
|
|
#define NV_SOR_PLL0_TXREG_LEVEL_V25 (0 << 12)
|
||
|
|
#define NV_SOR_PLL0_TXREG_LEVEL_V15 (1 << 12)
|
||
|
|
#define NV_SOR_PLL0_TXREG_LEVEL_V35 (2 << 12)
|
||
|
|
#define NV_SOR_PLL0_TXREG_LEVEL_V45 (3 << 12)
|
||
|
|
#define NV_SOR_PLL0_VCOCAP_SHIFT (8)
|
||
|
|
#define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK (0xf << 8)
|
||
|
|
#define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT (6)
|
||
|
|
#define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK (0x3 << 6)
|
||
|
|
#define NV_SOR_PLL0_PLLREG_LEVEL_V25 (0 << 6)
|
||
|
|
#define NV_SOR_PLL0_PLLREG_LEVEL_V15 (1 << 6)
|
||
|
|
#define NV_SOR_PLL0_PLLREG_LEVEL_V35 (2 << 6)
|
||
|
|
#define NV_SOR_PLL0_PLLREG_LEVEL_V45 (3 << 6)
|
||
|
|
#define NV_SOR_PLL0_PULLDOWN_SHIFT (5)
|
||
|
|
#define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK (0x1 << 5)
|
||
|
|
#define NV_SOR_PLL0_PULLDOWN_DISABLE (0 << 5)
|
||
|
|
#define NV_SOR_PLL0_PULLDOWN_ENABLE (1 << 5)
|
||
|
|
#define NV_SOR_PLL0_RESISTORSEL_SHIFT (4)
|
||
|
|
#define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK (0x1 << 4)
|
||
|
|
#define NV_SOR_PLL0_RESISTORSEL_INT (0 << 4)
|
||
|
|
#define NV_SOR_PLL0_RESISTORSEL_EXT (1 << 4)
|
||
|
|
#define NV_SOR_PLL0_VCOPD_SHIFT (2)
|
||
|
|
#define NV_SOR_PLL0_VCOPD_MASK (1 << 2)
|
||
|
|
#define NV_SOR_PLL0_VCOPD_RESCIND (0 << 2)
|
||
|
|
#define NV_SOR_PLL0_VCOPD_ASSERT (1 << 2)
|
||
|
|
#define NV_SOR_PLL0_PWR_SHIFT (0)
|
||
|
|
#define NV_SOR_PLL0_PWR_MASK (1)
|
||
|
|
#define NV_SOR_PLL0_PWR_ON (0)
|
||
|
|
#define NV_SOR_PLL0_PWR_OFF (1)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL1_COHERENTMODE (29)
|
||
|
|
#define NV_SOR_PLL1_COHERENTMODE_DEFAULT_MASK (0x1 << 29)
|
||
|
|
#define NV_SOR_PLL1_COHERENTMODE_DISABLE (0x0 << 29)
|
||
|
|
#define NV_SOR_PLL1_COHERENTMODE_ENABLE (0x1 << 29)
|
||
|
|
#define NV_SOR_PLL1_LVDSCM_SHIFT (24)
|
||
|
|
#define NV_SOR_PLL1_LVDSCM_DEFAULT_MASK (0x3 << 24)
|
||
|
|
#define NV_SOR_PLL1_LOADADJ_SHIFT (20)
|
||
|
|
#define NV_SOR_PLL1_LOADADJ_DEFAULT_MASK (0xf << 20)
|
||
|
|
#define NV_SOR_PLL1_TERM_COMPOUT_SHIFT (15)
|
||
|
|
#define NV_SOR_PLL1_TERM_COMPOUT_LOW (0 << 15)
|
||
|
|
#define NV_SOR_PLL1_TERM_COMPOUT_HIGH (1 << 15)
|
||
|
|
#define NV_SOR_PLL1_TMDS_TERMADJ_SHIFT (9)
|
||
|
|
#define NV_SOR_PLL1_TMDS_TERMADJ_OHM500 (8 << 9)
|
||
|
|
#define NV_SOR_PLL1_TMDS_TERMADJ_DEFAULT_MASK (0xf << 9)
|
||
|
|
#define NV_SOR_PLL1_TMDS_TERM_SHIFT (8)
|
||
|
|
#define NV_SOR_PLL1_TMDS_TERM_DISABLE (0 << 8)
|
||
|
|
#define NV_SOR_PLL1_TMDS_TERM_ENABLE (1 << 8)
|
||
|
|
#define NV_SOR_PLL1_TMDS_IOCURRENT (0)
|
||
|
|
#define NV_SOR_PLL1_TMDS_IOCURRENT_DEFAULT_MASK (0x1f << 0)
|
||
|
|
#define NV_SOR_PLL1_TMDS_IOCURRENT_RST (0)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT (0)
|
||
|
|
#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0)
|
||
|
|
#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW (1 << 0)
|
||
|
|
#define NV_SOR_PLL2_PLL_PDIV_MODE (2)
|
||
|
|
#define NV_SOR_PLL2_PLL_PDIV_MODE_MASK (0x3 << 4)
|
||
|
|
#define NV_SOR_PLL2_PLL_PDIV (4)
|
||
|
|
#define NV_SOR_PLL2_PLL_PDIV_MASK (0xf << 4)
|
||
|
|
#define NV_SOR_PLL2_PLL_NDIV (8)
|
||
|
|
#define NV_SOR_PLL2_PLL_NDIV_MASK (0xff << 8)
|
||
|
|
#define NV_SOR_PLL2_AUX0_SHIFT (16)
|
||
|
|
#define NV_SOR_PLL2_AUX0_MASK (1 << 16)
|
||
|
|
#define NV_SOR_PLL2_AUX0_SEQ_PLL_PULLDOWN_ALLOW (0 << 16)
|
||
|
|
#define NV_SOR_PLL2_AUX0_SEQ_PLL_PULLDOWN_OVERRIDE (1 << 16)
|
||
|
|
#define NV_SOR_PLL2_AUX1_SHIFT (17)
|
||
|
|
#define NV_SOR_PLL2_AUX1_SEQ_MASK (1 << 17)
|
||
|
|
#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17)
|
||
|
|
#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17)
|
||
|
|
#define NV_SOR_PLL2_AUX2_SHIFT (18)
|
||
|
|
#define NV_SOR_PLL2_AUX2_MASK (1 << 18)
|
||
|
|
#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18)
|
||
|
|
#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN (1 << 18)
|
||
|
|
#define NV_SOR_PLL2_AUX3_SHIFT (19)
|
||
|
|
#define NV_SOR_PLL2_AUX3_MASK (1 << 19)
|
||
|
|
#define NV_SOR_PLL2_AUX3_ROTATE_DISABLE (0 << 19)
|
||
|
|
#define NV_SOR_PLL2_AUX3_ROTATE_ENABLE (1 << 19)
|
||
|
|
#define NV_SOR_PLL2_AUX6_SHIFT (22)
|
||
|
|
#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22)
|
||
|
|
#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22)
|
||
|
|
#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22)
|
||
|
|
#define NV_SOR_PLL2_AUX7_SHIFT (23)
|
||
|
|
#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23)
|
||
|
|
#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23)
|
||
|
|
#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23)
|
||
|
|
#define NV_SOR_PLL2_AUX8_SHIFT (24)
|
||
|
|
#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24)
|
||
|
|
#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24)
|
||
|
|
#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24)
|
||
|
|
#define NV_SOR_PLL2_AUX9_SHIFT (25)
|
||
|
|
#define NV_SOR_PLL2_AUX9_LVDSEN_ALLOW (0 << 25)
|
||
|
|
#define NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25)
|
||
|
|
#define NV_SOR_PLL2_CLKGEN_MODE (26)
|
||
|
|
#define NV_SOR_PLL2_CLKGEN_MODE_MASK (0x3 << 26)
|
||
|
|
#define NV_SOR_PLL2_CLKGEN_MODE_DP_TMDS (1 << 26)
|
||
|
|
#define NV_SOR_PLL2_CLKGEN_MODE_LVDS (0 << 26)
|
||
|
|
#define NV_SOR_PLL2_PLL_MDIV (28)
|
||
|
|
#define NV_SOR_PLL2_PLL_MDIV_MASK (0xf << 28)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL3_BG_TEMP_COEFF_SHIFT (28)
|
||
|
|
#define NV_SOR_PLL3_BG_TEMP_COEFF_MASK (0xf << 28)
|
||
|
|
#define NV_SOR_PLL3_BG_VREF_LEVEL_SHIFT (24)
|
||
|
|
#define NV_SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24)
|
||
|
|
#define NV_SOR_PLL3_PLL_BYPASS_SHIFT (14)
|
||
|
|
#define NV_SOR_PLL3_PLL_BYPASS_MASK (1 << 14)
|
||
|
|
#define NV_SOR_PLL3_PLL_BYPASS_DISABLE (0 << 14)
|
||
|
|
#define NV_SOR_PLL3_PLL_BYPASS_ENABLE (1 << 14)
|
||
|
|
#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT (13)
|
||
|
|
#define NV_SOR_PLL3_PLLVDD_MODE_MASK (1 << 13)
|
||
|
|
#define NV_SOR_PLL3_PLLVDD_MODE_V1_8 (0 << 13)
|
||
|
|
#define NV_SOR_PLL3_PLLVDD_MODE_V3_3 (1 << 13)
|
||
|
|
|
||
|
|
#define NV_SOR_PLL4_LOCKDET_SHIFT (21)
|
||
|
|
#define NV_SOR_PLL4_LOCKDET_MASK (1 << 21)
|
||
|
|
|
||
|
|
#define NV_SOR_DP_MISC1_OVERRIDE (0x16d)
|
||
|
|
#define NV_SOR_DP_MISC1_OVERRIDE_ENABLE (1)
|
||
|
|
#define NV_SOR_DP_MISC1_OVERRIDE_DISABLE (0)
|
||
|
|
#define NV_SOR_DP_MISC1_OVERRIDE_CNTL_DONE (0 << 31)
|
||
|
|
#define NV_SOR_DP_MISC1_OVERRIDE_CNTL_TRIGGER (1 << 31)
|
||
|
|
|
||
|
|
#define NV_SOR_DP_MISC1_BIT6_0 (0x16e)
|
||
|
|
#define NV_SOR_DP_MISC1_BIT6_0_SET (1)
|
||
|
|
|
||
|
|
#define NV_SOR_CSTM (0x1b)
|
||
|
|
#define NV_SOR_CSTM_ROTDAT_SHIFT (28)
|
||
|
|
#define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK (0x7 << 28)
|
||
|
|
#define NV_SOR_CSTM_ROTCLK_SHIFT (24)
|
||
|
|
#define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK (0xf << 24)
|
||
|
|
#define NV_SOR_CSTM_PLLDIV_SHIFT (21)
|
||
|
|
#define NV_SOR_CSTM_PLLDIV_DEFAULT_MASK (0x1 << 21)
|
||
|
|
#define NV_SOR_CSTM_LVDS_EN_SHIFT (16)
|
||
|
|
#define NV_SOR_CSTM_LVDS_EN_DISABLE (0 << 16)
|
||
|
|
#define NV_SOR_CSTM_LVDS_EN_ENABLE (1 << 16)
|
||
|
|
#define NV_SOR_CSTM_LINKACTB_SHIFT (15)
|
||
|
|
#define NV_SOR_CSTM_LINKACTB_DISABLE (0 << 15)
|
||
|
|
#define NV_SOR_CSTM_LINKACTB_ENABLE (1 << 15)
|
||
|
|
#define NV_SOR_CSTM_LINKACTA_SHIFT (14)
|
||
|
|
#define NV_SOR_CSTM_LINKACTA_DISABLE (0 << 14)
|
||
|
|
#define NV_SOR_CSTM_LINKACTA_ENABLE (1 << 14)
|
||
|
|
#define NV_SOR_LVDS (0x1c)
|
||
|
|
#define NV_SOR_LVDS_ROTDAT_SHIFT (28)
|
||
|
|
#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK (0x7 << 28)
|
||
|
|
#define NV_SOR_LVDS_ROTDAT_RST (0 << 28)
|
||
|
|
#define NV_SOR_LVDS_ROTCLK_SHIFT (24)
|
||
|
|
#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK (0xf << 24)
|
||
|
|
#define NV_SOR_LVDS_ROTCLK_RST (0 << 24)
|
||
|
|
#define NV_SOR_LVDS_PLLDIV_SHIFT (21)
|
||
|
|
#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK (0x1 << 21)
|
||
|
|
#define NV_SOR_LVDS_PLLDIV_BY_7 (0 << 21)
|
||
|
|
#define NV_SOR_LVDS_BALANCED_SHIFT (19)
|
||
|
|
#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK (0x1 << 19)
|
||
|
|
#define NV_SOR_LVDS_BALANCED_DISABLE (0 << 19)
|
||
|
|
#define NV_SOR_LVDS_BALANCED_ENABLE (1 << 19)
|
||
|
|
#define NV_SOR_LVDS_NEW_MODE_SHIFT (18)
|
||
|
|
#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK (0x1 << 18)
|
||
|
|
#define NV_SOR_LVDS_NEW_MODE_DISABLE (0 << 18)
|
||
|
|
#define NV_SOR_LVDS_NEW_MODE_ENABLE (1 << 18)
|
||
|
|
#define NV_SOR_LVDS_DUP_SYNC_SHIFT (17)
|
||
|
|
#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK (0x1 << 17)
|
||
|
|
#define NV_SOR_LVDS_DUP_SYNC_DISABLE (0 << 17)
|
||
|
|
#define NV_SOR_LVDS_DUP_SYNC_ENABLE (1 << 17)
|
||
|
|
#define NV_SOR_LVDS_LVDS_EN_SHIFT (16)
|
||
|
|
#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK (0x1 << 16)
|
||
|
|
#define NV_SOR_LVDS_LVDS_EN_ENABLE (1 << 16)
|
||
|
|
#define NV_SOR_LVDS_LINKACTB_SHIFT (15)
|
||
|
|
#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK (0x1 << 15)
|
||
|
|
#define NV_SOR_LVDS_LINKACTB_DISABLE (0 << 15)
|
||
|
|
#define NV_SOR_LVDS_LINKACTB_ENABLE (1 << 15)
|
||
|
|
#define NV_SOR_LVDS_LINKACTA_SHIFT (14)
|
||
|
|
#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK (0x1 << 14)
|
||
|
|
#define NV_SOR_LVDS_LINKACTA_ENABLE (1 << 14)
|
||
|
|
#define NV_SOR_LVDS_MODE_SHIFT (12)
|
||
|
|
#define NV_SOR_LVDS_MODE_DEFAULT_MASK (0x3 << 12)
|
||
|
|
#define NV_SOR_LVDS_MODE_LVDS (0 << 12)
|
||
|
|
#define NV_SOR_LVDS_UPPER_SHIFT (11)
|
||
|
|
#define NV_SOR_LVDS_UPPER_DEFAULT_MASK (0x1 << 11)
|
||
|
|
#define NV_SOR_LVDS_UPPER_FALSE (0 << 11)
|
||
|
|
#define NV_SOR_LVDS_UPPER_TRUE (1 << 11)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCB_SHIFT (9)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK (0x1 << 9)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCB_ENABLE (0 << 9)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCB_DISABLE (1 << 9)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCA_SHIFT (8)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK (0x1 << 8)
|
||
|
|
#define NV_SOR_LVDS_PD_TXCA_ENABLE (0 << 8)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_3_SHIFT (7)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK (0x1 << 7)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_3_ENABLE (0 << 7)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_3_DISABLE (1 << 7)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_2_SHIFT (6)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK (0x1 << 6)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_2_ENABLE (0 << 6)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_2_DISABLE (1 << 6)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_1_SHIFT (5)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK (0x1 << 5)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_1_ENABLE (0 << 5)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_1_DISABLE (1 << 5)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_0_SHIFT (4)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK (0x1 << 4)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_0_ENABLE (0 << 4)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDB_0_DISABLE (1 << 4)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_3_SHIFT (3)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK (0x1 << 3)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_3_ENABLE (0 << 3)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_3_DISABLE (1 << 3)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_2_SHIFT (2)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK (0x1 << 2)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_2_ENABLE (0 << 2)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_1_SHIFT (1)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK (0x1 << 1)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_1_ENABLE (0 << 1)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_0_SHIFT (0)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK (0x1)
|
||
|
|
#define NV_SOR_LVDS_PD_TXDA_0_ENABLE (0)
|
||
|
|
#define NV_SOR_CRCA (0x1d)
|
||
|
|
#define NV_SOR_CRCA_VALID_SHIFT (0)
|
||
|
|
#define NV_SOR_CRCA_VALID_DEFAULT_MASK (1)
|
||
|
|
#define NV_SOR_CRCA_VALID_FALSE (0)
|
||
|
|
#define NV_SOR_CRCA_VALID_TRUE (1)
|
||
|
|
#define NV_SOR_CRCA_VALID_RST (1)
|
||
|
|
#define NV_SOR_CRCB (0x1e)
|
||
|
|
#define NV_SOR_CRCB_CRC_DEFAULT_MASK (0xffffffff)
|
||
|
|
#define NV_SOR_SEQ_CTL (0x20)
|
||
|
|
#define NV_SOR_SEQ_CTL_SWITCH_SHIFT (30)
|
||
|
|
#define NV_SOR_SEQ_CTL_SWITCH_MASK (0x1 << 30)
|
||
|
|
#define NV_SOR_SEQ_CTL_SWITCH_WAIT (0 << 30)
|
||
|
|
#define NV_SOR_SEQ_CTL_SWITCH_FORCE (1 << 30)
|
||
|
|
#define NV_SOR_SEQ_CTL_STATUS_SHIFT (28)
|
||
|
|
#define NV_SOR_SEQ_CTL_STATUS_MASK (0x1 << 28)
|
||
|
|
#define NV_SOR_SEQ_CTL_STATUS_STOPPED (0 << 28)
|
||
|
|
#define NV_SOR_SEQ_CTL_STATUS_RUNNING (1 << 28)
|
||
|
|
#define NV_SOR_SEQ_CTL_PC_SHIFT (16)
|
||
|
|
#define NV_SOR_SEQ_CTL_PC_MASK (0xf << 16)
|
||
|
|
#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT (12)
|
||
|
|
#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK (0xf << 12)
|
||
|
|
#define NV_SOR_SEQ_CTL_PD_PC_SHIFT (8)
|
||
|
|
#define NV_SOR_SEQ_CTL_PD_PC_MASK (0xf << 8)
|
||
|
|
#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT (4)
|
||
|
|
#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK (0xf << 4)
|
||
|
|
#define NV_SOR_SEQ_CTL_PU_PC_SHIFT (0)
|
||
|
|
#define NV_SOR_SEQ_CTL_PU_PC_MASK (0xf)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL (0x21)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT (31)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK (1 << 31)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT (28)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT (20)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT (16)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT (12)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT (9)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT (8)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT (7)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT (6)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT (5)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT (4)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT (3)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT (2)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT (1)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT (0)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP (0)
|
||
|
|
#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN (1)
|
||
|
|
|
||
|
|
#define NV_SOR_SEQ_INST(i) (0x22 + i)
|
||
|
|
#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT (31)
|
||
|
|
#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31)
|
||
|
|
#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31)
|
||
|
|
#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT (30)
|
||
|
|
#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30)
|
||
|
|
#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30)
|
||
|
|
#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT (29)
|
||
|
|
#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29)
|
||
|
|
#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_V_SHIFT (28)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_V_NORMAL (0 << 28)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE (1 << 28)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_H_SHIFT (27)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_H_NORMAL (0 << 27)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE (1 << 27)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT (26)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL (0 << 26)
|
||
|
|
#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE (1 << 26)
|
||
|
|
#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT (25)
|
||
|
|
#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL (0 << 25)
|
||
|
|
#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK (1 << 25)
|
||
|
|
#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT (24)
|
||
|
|
#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24)
|
||
|
|
#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24)
|
||
|
|
#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT (23)
|
||
|
|
#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23)
|
||
|
|
#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23)
|
||
|
|
#define NV_SOR_SEQ_INST_PIN_B_SHIFT (22)
|
||
|
|
#define NV_SOR_SEQ_INST_PIN_B_LOW (0 << 22)
|
||
|
|
#define NV_SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
|
||
|
|
#define NV_SOR_SEQ_INST_PIN_A_SHIFT (21)
|
||
|
|
#define NV_SOR_SEQ_INST_PIN_A_LOW (0 << 21)
|
||
|
|
#define NV_SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
|
||
|
|
#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT (19)
|
||
|
|
#define NV_SOR_SEQ_INST_SEQUENCE_UP (0 << 19)
|
||
|
|
#define NV_SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19)
|
||
|
|
#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT (18)
|
||
|
|
#define NV_SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18)
|
||
|
|
#define NV_SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18)
|
||
|
|
#define NV_SOR_SEQ_INST_PDPORT_SHIFT (17)
|
||
|
|
#define NV_SOR_SEQ_INST_PDPORT_NO (0 << 17)
|
||
|
|
#define NV_SOR_SEQ_INST_PDPORT_YES (1 << 17)
|
||
|
|
#define NV_SOR_SEQ_INST_PDPLL_SHIFT (16)
|
||
|
|
#define NV_SOR_SEQ_INST_PDPLL_NO (0 << 16)
|
||
|
|
#define NV_SOR_SEQ_INST_PDPLL_YES (1 << 16)
|
||
|
|
#define NV_SOR_SEQ_INST_HALT_SHIFT (15)
|
||
|
|
#define NV_SOR_SEQ_INST_HALT_FALSE (0 << 15)
|
||
|
|
#define NV_SOR_SEQ_INST_HALT_TRUE (1 << 15)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT (12)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK (0x3 << 12)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_UNITS_US (0 << 12)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT (0)
|
||
|
|
#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK (0x3ff)
|
||
|
|
#define NV_SOR_PWM_DIV (0x32)
|
||
|
|
#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK (0xffffff)
|
||
|
|
#define NV_SOR_PWM_CTL (0x33)
|
||
|
|
#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT (31)
|
||
|
|
#define NV_SOR_PWM_CTL_SETTING_NEW_DONE (0 << 31)
|
||
|
|
#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING (1 << 31)
|
||
|
|
#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER (1 << 31)
|
||
|
|
#define NV_SOR_PWM_CTL_CLKSEL_SHIFT (30)
|
||
|
|
#define NV_SOR_PWM_CTL_CLKSEL_PCLK (0 << 30)
|
||
|
|
#define NV_SOR_PWM_CTL_CLKSEL_XTAL (1 << 30)
|
||
|
|
#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT (0)
|
||
|
|
#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK (0xffffff)
|
||
|
|
#define NV_SOR_MSCHECK (0x49)
|
||
|
|
#define NV_SOR_MSCHECK_CTL_SHIFT (31)
|
||
|
|
#define NV_SOR_MSCHECK_CTL_CLEAR (0 << 31)
|
||
|
|
#define NV_SOR_MSCHECK_CTL_RUN (1 << 31)
|
||
|
|
#define NV_SOR_XBAR_CTRL (0x4a)
|
||
|
|
#define NV_SOR_XBAR_BYPASS_MASK (1 << 0)
|
||
|
|
#define NV_SOR_XBAR_LINK_SWAP_MASK (1 << 1)
|
||
|
|
#define NV_SOR_XBAR_LINK_XSEL_MASK (0x7)
|
||
|
|
#define NV_SOR_XBAR_POL (0x4b)
|
||
|
|
#define NV_SOR_DP_LINKCTL(i) (0x4c + (i))
|
||
|
|
#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT (31)
|
||
|
|
#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31)
|
||
|
|
#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31)
|
||
|
|
#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT (28)
|
||
|
|
#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28)
|
||
|
|
#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28)
|
||
|
|
#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT (16)
|
||
|
|
#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK (0x1f << 16)
|
||
|
|
#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO (0 << 16)
|
||
|
|
#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE (1 << 16)
|
||
|
|
#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO (3 << 16)
|
||
|
|
#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR (15 << 16)
|
||
|
|
#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT (14)
|
||
|
|
#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14)
|
||
|
|
#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14)
|
||
|
|
#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT (10)
|
||
|
|
#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE (0 << 10)
|
||
|
|
#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE (1 << 10)
|
||
|
|
#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT (2)
|
||
|
|
#define NV_SOR_DP_LINKCTL_TUSIZE_MASK (0x7f << 2)
|
||
|
|
#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_LINKCTL_ENABLE_NO (0)
|
||
|
|
#define NV_SOR_DP_LINKCTL_ENABLE_YES (1)
|
||
|
|
#define NV_SOR_DC(i) (0x4e + (i))
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT (24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_MASK (0xff << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24)
|
||
|
|
#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT (16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_MASK (0xff << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16)
|
||
|
|
#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT (8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_MASK (0xff << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8)
|
||
|
|
#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT (0)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_MASK (0xff)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0 (17)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 (21)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0 (26)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0 (34)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1 (26)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1 (32)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1 (39)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2 (34)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43)
|
||
|
|
#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51)
|
||
|
|
#define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i))
|
||
|
|
#define NV_SOR_LANE4_DRIVE_CURRENT(i) (0x50 + (i))
|
||
|
|
#define NV_SOR_PR(i) (0x52 + (i))
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24)
|
||
|
|
#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT (16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_MASK (0xff << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16)
|
||
|
|
#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT (8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_MASK (0xff << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0 (0 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0 (0 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0 (0 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0 (0 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1 (4 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1 (6 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1 (17 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2 (8 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2 (13 << 8)
|
||
|
|
#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3 (17 << 8)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT (0)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_MASK (0xff)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0 (0)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0 (0)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0 (0)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0 (0)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1 (4)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1 (6)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1 (17)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2 (8)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2 (13)
|
||
|
|
#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3 (17)
|
||
|
|
#define NV_SOR_LANE4_PREEMPHASIS(i) (0x54 + (i))
|
||
|
|
#define NV_SOR_POSTCURSOR(i) (0x56 + (i))
|
||
|
|
#define NV_SOR_DP_CONFIG(i) (0x58 + (i))
|
||
|
|
#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT (31)
|
||
|
|
#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31)
|
||
|
|
#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31)
|
||
|
|
#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT (28)
|
||
|
|
#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28)
|
||
|
|
#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT (26)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT (24)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT (16)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT (8)
|
||
|
|
#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8)
|
||
|
|
#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_CONFIG_WATERMARK_MASK (0x3f)
|
||
|
|
#define NV_SOR_DP_MN(i) (0x5a + i)
|
||
|
|
#define NV_SOR_DP_MN_M_MOD_SHIFT (30)
|
||
|
|
#define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK (0x3 << 30)
|
||
|
|
#define NV_SOR_DP_MN_M_MOD_NONE (0 << 30)
|
||
|
|
#define NV_SOR_DP_MN_M_MOD_INC (1 << 30)
|
||
|
|
#define NV_SOR_DP_MN_M_MOD_DEC (2 << 30)
|
||
|
|
#define NV_SOR_DP_MN_M_DELTA_SHIFT (24)
|
||
|
|
#define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24)
|
||
|
|
#define NV_SOR_DP_MN_N_VAL_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK (0xffffff)
|
||
|
|
|
||
|
|
#define NV_SOR_DP_PADCTL_T18X(i) (0x168 + (i))
|
||
|
|
#define NV_SOR_DP_PADCTL(i) (0x5c + (i))
|
||
|
|
|
||
|
|
#define NV_SOR_DP_PADCTL_SPARE_SHIFT (25)
|
||
|
|
#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT (24)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE (0 << 24)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE (1 << 24)
|
||
|
|
#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT (23)
|
||
|
|
#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23)
|
||
|
|
#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
|
||
|
|
#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20)
|
||
|
|
#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE (0 << 16)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX (1 << 16)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16)
|
||
|
|
#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT (8)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_VALUE_RBR_HBR (0x10 << 8)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_VALUE_HBR2 (0x20 << 8)
|
||
|
|
#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT (7)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT (6)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT (5)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT (4)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4)
|
||
|
|
#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT (3)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_3_YES (0 << 3)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_3_NO (1 << 3)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT (2)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_0_YES (0 << 2)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_0_NO (1 << 2)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT (1)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_1_YES (0 << 1)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_1_NO (1 << 1)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_2_YES (0)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_2_NO (1)
|
||
|
|
#define NV_SOR_DP_PADCTL_PD_TXD_MASK (0xf)
|
||
|
|
#define NV_SOR_DP_DEBUG(i) (0x5e + i)
|
||
|
|
#define NV_SOR_DP_SPARE(i) (0x60 + (i))
|
||
|
|
#define NV_SOR_DP_SPARE_MSA_SRC_RG (1 << 30)
|
||
|
|
#define NV_SOR_DP_SPARE_MSA_SRC_SOR (0 << 30)
|
||
|
|
#define NV_SOR_DP_SPARE_MSA_SRC_MASK (1 << 30)
|
||
|
|
#define NV_SOR_DP_SPARE_REG_SHIFT (3)
|
||
|
|
#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3)
|
||
|
|
#define NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_MASK (1 << 3)
|
||
|
|
#define NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_ENABLE (1 << 3)
|
||
|
|
#define NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_DISABLE (0 << 3)
|
||
|
|
#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT (2)
|
||
|
|
#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (0x1 << 2)
|
||
|
|
#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2)
|
||
|
|
#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2)
|
||
|
|
#define NV_SOR_DP_SPARE_PANEL_MASK (1 << 1)
|
||
|
|
#define NV_SOR_DP_SPARE_PANEL_SHIFT (1)
|
||
|
|
#define NV_SOR_DP_SPARE_PANEL_EXTERNAL (0 << 1)
|
||
|
|
#define NV_SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
|
||
|
|
#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO (0)
|
||
|
|
#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES (1)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL (0x62)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_ENABLE (1)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_NEW_SETTINGS_TRIGGER (1 << 31)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_CA_SELECT_HW (1 << 20)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_SS_SELECT_HW (1 << 19)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_SF_SELECT_HW (1 << 18)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_CC_SELECT_HW (1 << 17)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_CT_SELECT_HW (1 << 16)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_GENERIC_INFOFRAME_ENABLE (1 << 7)
|
||
|
|
#define NV_SOR_DP_AUDIO_CTRL_GENERIC_INFOFRAME_DISABLE (0 << 7)
|
||
|
|
#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS (0x63)
|
||
|
|
#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x1ffff)
|
||
|
|
#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS (0x64)
|
||
|
|
#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1ffff)
|
||
|
|
#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER (0x65)
|
||
|
|
#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i))
|
||
|
|
#define NV_SOR_DP_TPG (0x6d)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT (30)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT (28)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT (24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_D102 (4 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM (7 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT1 (9 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT3 (10 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING4 (11 << 24)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT (22)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT (20)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (0x3 << 20)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT (16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_D102 (4 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM (7 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT1 (9 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT3 (10 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING4 (11 << 16)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT (14)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT (12)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (0x3 << 12)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT (8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_D102 (4 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM (7 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT1 (9 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT3 (10 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING4 (11 << 8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT (6)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT (4)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (0x3 << 4)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT (0)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK (0xf)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN (0)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 (1)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 (2)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 (3)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_D102 (4)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE (5)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7 (6)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM (7)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE (8)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT1 (9)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT3 (10)
|
||
|
|
#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING4 (11)
|
||
|
|
#define NV_SOR_DP_TPG_CONFIG (0x6e)
|
||
|
|
#define NV_SOR_DP_LQ_CSTM_0 (0x6f)
|
||
|
|
#define NV_SOR_DP_LQ_CSTM_1 (0x70)
|
||
|
|
#define NV_SOR_DP_LQ_CSTM_2 (0x71)
|
||
|
|
|
||
|
|
#define NV_SOR_DP_INT_ENABLE 0x171
|
||
|
|
|
||
|
|
/* Specific to Nvdisplay */
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL (0x173)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_MODE_FIELD (1 << 0)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_MODE_HDMI (0 << 0)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_OUT_EN_FIELD (1 << 1)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_OUT_EN_ENABLE (1 << 1)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_MODE_FIELD (1 << 2)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_MODE_HDMI (0 << 2)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_OUT_EN_FIELD (1 << 3)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_OUT_EN_ENABLE (1 << 3)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_MODE_FIELD (1 << 4)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_MODE_HDMI (0 << 4)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_OUT_EN_FIELD (1 << 5)
|
||
|
|
#define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_OUT_EN_ENABLE (1 << 5)
|
||
|
|
|
||
|
|
#define NV_SOR_FPGA_DISPCLK_HEAD_SEL (0x174)
|
||
|
|
/* Nvdisplay specific registers end here */
|
||
|
|
|
||
|
|
#define NV_SOR_HDMI_ACR_CTRL 0xb1
|
||
|
|
#define NV_SOR_HDMI_ACR_0320_SUBPACK_LOW 0xb2
|
||
|
|
#define NV_SOR_HDMI_ACR_0320_SUBPACK_HIGH 0xb3
|
||
|
|
#define NV_SOR_HDMI_ACR_0441_SUBPACK_LOW 0xb4
|
||
|
|
#define NV_SOR_HDMI_ACR_0441_SUBPACK_HIGH 0xb5
|
||
|
|
#define NV_SOR_HDMI_ACR_SB3(x) (((x) & 0xff) << 8)
|
||
|
|
#define NV_SOR_HDMI_ACR_SB2(x) (((x) & 0xff) << 16)
|
||
|
|
#define NV_SOR_HDMI_ACR_SB1(x) (((x) & 0xff) << 24)
|
||
|
|
#define NV_SOR_HDMI_ACR_SB6(x) (((x) & 0xff) << 0)
|
||
|
|
#define NV_SOR_HDMI_ACR_SB5(x) (((x) & 0xff) << 8)
|
||
|
|
#define NV_SOR_HDMI_ACR_SB4(x) (((x) & 0xff) << 16)
|
||
|
|
#define NV_SOR_HDMI_ACR_SUBPACK_ENABLE (1 << 31)
|
||
|
|
#define NV_SOR_HDMI_ACR_SUBPACK_USE_HW_CTS NV_SOR_HDMI_ACR_SB1(0)
|
||
|
|
#define NV_SOR_HDMI_SPARE 0xcb
|
||
|
|
#define NV_SOR_HDMI_SPARE_HW_CTS_ENABLE (1 << 0)
|
||
|
|
#define NV_SOR_HDMI_SPARE_HW_CTS_DISABLE (0 << 0)
|
||
|
|
#define NV_SOR_HDMI_SPARE_FORCE_SW_CTS (1 << 1)
|
||
|
|
#define NV_SOR_HDMI_SPARE_SUPRESS_SP_B (1 << 2)
|
||
|
|
#define NV_SOR_HDMI_SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
|
||
|
|
#define NV_SOR_HDMI_SPARE_ACR_PRIORITY_HIGH (0 << 31)
|
||
|
|
#define NV_SOR_HDMI_SPARE_ACR_PRIORITY_LOW (1 << 31)
|
||
|
|
#define NV_SOR_HDMI_GCP_CTRL (0xc3)
|
||
|
|
#define NV_SOR_HDMI_GCP_CTRL_ENABLE (1)
|
||
|
|
#define NV_SOR_HDMI_GCP_CTRL_DISABLE (0)
|
||
|
|
#define NV_SOR_HDMI_GCP_CTRL_OTHER_DIS (0 << 4)
|
||
|
|
#define NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS (0 << 8)
|
||
|
|
#define NV_SOR_HDMI_GCP_STATUS (0xc4)
|
||
|
|
#define NV_SOR_HDMI_GCP_STATUS_ACTIVE_END_PP_SHIFT (8)
|
||
|
|
#define NV_SOR_HDMI_GCP_STATUS_ACTIVE_END_PP_MASK (0x7)
|
||
|
|
#define NV_SOR_HDMI_GCP_SUBPACK(i) (0xc5 + i)
|
||
|
|
#define NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT (8)
|
||
|
|
#define NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT (16)
|
||
|
|
#define NV_SOR_INPUT_CONTROL 0xe8
|
||
|
|
#define NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL (0 << 1)
|
||
|
|
#define NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)
|
||
|
|
#define NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAY (0 << 0)
|
||
|
|
#define NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB (1 << 0)
|
||
|
|
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_CHECKSUM_ENABLE (1 << 9)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_CHECKSUM_DISABLE (0 << 9)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE_ENABLE (1 << 8)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE_DISABLE (0 << 8)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_OTHER_ENABLE (1 << 4)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_OTHER_DISABLE (0 << 4)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE_YES (1)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE_NO (0)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x9d
|
||
|
|
#define NV_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x9e
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_HEADER 0xa1
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0xa2
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0xa3
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0 0xa4
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0 0xa5
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL 0x9f
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE (1 << 9)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_DISABLE (0 << 9)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_ENABLE (1 << 8)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE (0 << 8)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_ENABLE (1 << 4)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE (0 << 4)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES (1)
|
||
|
|
#define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO (0)
|
||
|
|
|
||
|
|
#define NV_SOR_REFCLK 0xe6
|
||
|
|
#define NV_SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
|
||
|
|
#define NV_SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6)
|
||
|
|
#define NV_SOR_AUDIO_CTRL 0xfc
|
||
|
|
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL 0xa6
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_AUDIO_ENABLE (1 << 16)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_AUDIO_DISABLE (0 << 16)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_HBLANK_ENABLE (1 << 12)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_HBLANK_DISABLE (0 << 12)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_SINGLE_ENABLE (1 << 8)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_SINGLE_DISABLE (0 << 8)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_OTHER_ENABLE (1 << 4)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_OTHER_DISABLE (0 << 4)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES (1 << 0)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_CTRL_ENABLE_NO (0 << 0)
|
||
|
|
#define NV_SOR_HDMI_GENERIC_HEADER 0xa8
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK0_LOW 0xa9
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK0_HIGH 0xaa
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK1_LOW 0xab
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK1_HIGH 0xac
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK2_LOW 0xad
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK2_HIGH 0xae
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK3_LOW 0xaf
|
||
|
|
#define NV_SOR_HDMI_GENERIC_SUBPACK3_HIGH 0xb0
|
||
|
|
#define NV_SOR_AUDIO_CTRL_AFIFO_FLUSH (1 << 12)
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#define NV_SOR_AUDIO_CTRL_SRC_HDA (0x2 << 20)
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#define NV_SOR_AUDIO_CTRL_NULL_SAMPLE_EN (1 << 29)
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#define NV_SOR_AUDIO_CTRL_NULL_SAMPLE_DIS (0 << 29)
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#define NV_SOR_AUDIO_DEBUG 0xfd
|
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#define NV_SOR_AUDIO_NVAL_0320 0xff
|
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#define NV_SOR_AUDIO_NVAL_0441 0x100
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#define NV_SOR_AUDIO_NVAL_0882 0x101
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#define NV_SOR_AUDIO_NVAL_1764 0x102
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#define NV_SOR_AUDIO_NVAL_0480 0x103
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#define NV_SOR_AUDIO_NVAL_0960 0x104
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#define NV_SOR_AUDIO_NVAL_1920 0x105
|
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#define NV_SOR_SEQ_INST0 0x22
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#define NV_SOR_SEQ_INST8 0x2a
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#define NV_SOR_HDMI_CTRL 0xc0
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#define NV_SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
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#define NV_SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 8)
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#define NV_SOR_HDMI_CTRL_SAMPLE_FLAT (1 << 12)
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#define NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT (1 << 10)
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#define NV_SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
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#define NV_SOR_HDMI_CTRL_ENABLE (1 << 30)
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#define NV_SOR_AUDIO_HDA_ELD_BUFWR (0x10c)
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#define NV_SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x) (((x) & 0xff) << 8)
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#define NV_SOR_AUDIO_HDA_ELD_BUFWR_DATA(x) (((x) & 0xff) << 0)
|
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#define NV_SOR_AUDIO_HDA_PRESENCE (0x10d)
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#define NV_SOR_AUDIO_HDA_PRESENCE_ELDV(x) ((x) << 1)
|
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#define NV_SOR_AUDIO_HDA_PRESENCE_PD(x) (x)
|
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#define NV_SOR_AUDIO_AVAL_0320 0x10f
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#define NV_SOR_AUDIO_AVAL_0441 0x110
|
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#define NV_SOR_AUDIO_AVAL_0882 0x111
|
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#define NV_SOR_AUDIO_AVAL_1764 0x112
|
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#define NV_SOR_AUDIO_AVAL_0480 0x113
|
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#define NV_SOR_AUDIO_AVAL_0960 0x114
|
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#define NV_SOR_AUDIO_AVAL_1920 0x115
|
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#define NV_SOR_AUDIO_GEN_CTRL 0x117
|
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#define NV_SOR_AUDIO_GEN_CTRL_DEV_ID_SHIFT (16)
|
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#define NV_SOR_AUDIO_GEN_CTRL_DEV_ID_MASK (0xffff)
|
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|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL 0x123
|
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|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE (1 << 9)
|
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|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_DISABLE (0 << 9)
|
||
|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_ENABLE (1 << 8)
|
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|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE (0 << 8)
|
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|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_ENABLE (1 << 4)
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE (0 << 4)
|
||
|
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#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES (1)
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_NO (0)
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW 0x126
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH 0x127
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW 0x128
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH 0x129
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW 0x12a
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH 0x12b
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW 0x12c
|
||
|
|
#define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH 0x12d
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N 0x13c
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N_RESET_ASSERT (1 << 20)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N_RESET_DEASSERT (0 << 20)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N_GENERATE_NORMAL (0 << 24)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N_GENERATE_ALTERNALTE (1 << 24)
|
||
|
|
#define NV_SOR_HDMI_AUDIO_N_LOOKUP_ENABLE (1 << 28)
|
||
|
|
|
||
|
|
#define NV_SOR_DP_AUDIO_CRC 0x12e
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_0320 0x133
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_0441 0x134
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_0882 0x135
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_1764 0x136
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_0480 0x137
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_0960 0x138
|
||
|
|
#define NV_SOR_DP_AUDIO_TIMESTAMP_1920 0x139
|
||
|
|
#define NV_SOR_DP_OUTPUT_CHANNEL_STATUS1 0x13a
|
||
|
|
#define NV_SOR_DP_OUTPUT_CHANNEL_STATUS2 0x13b
|
||
|
|
#define NV_SOR_DP_OUTPUT_CHANNEL_STATUS2_OVERRIDE_EN (1 << 31)
|
||
|
|
#define NV_SOR_DP_OUTPUT_CHANNEL_STATUS2_OVERRIDE_DIS (0 << 31)
|
||
|
|
|
||
|
|
#define NV_SOR_HDMI2_CTRL 0x13e
|
||
|
|
#define NV_SOR_HDMI2_CTRL_SSCP_START (0x214 << 16)
|
||
|
|
#define NV_SOR_HDMI2_CTRL_SSCP_START_MASK (0xffff << 16)
|
||
|
|
#define NV_SOR_HDMI2_CTRL_SSCP_LEN (0x8 << 4)
|
||
|
|
#define NV_SOR_HDMI2_CTRL_CLK_MODE_NORMAL (0 << 1)
|
||
|
|
#define NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4 (1 << 1)
|
||
|
|
#define NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE (1)
|
||
|
|
#define NV_SOR_HDMI2_CTRL_SCRAMBLE_DISABLE (0)
|
||
|
|
|
||
|
|
#define NV_SOR_DP_HDCP_AN_MSB (0x75)
|
||
|
|
#define NV_SOR_DP_HDCP_AN_LSB (0x76)
|
||
|
|
#define NV_SOR_DP_HDCP_AKSV_MSB (0x77)
|
||
|
|
#define NV_SOR_DP_HDCP_AKSV_LSB (0x78)
|
||
|
|
#define NV_SOR_DP_HDCP_BKSV_MSB (0x79)
|
||
|
|
#define NV_SOR_DP_HDCP_BKSV_LSB (0x7a)
|
||
|
|
#define NV_SOR_DP_HDCP_CTRL (0x7b)
|
||
|
|
#define NV_SOR_DP_HDCP_RI (0x7c)
|
||
|
|
#define NV_SOR_DP_HDCP_CYA (0x7f)
|
||
|
|
|
||
|
|
#define NV_SOR_TMDS_HDCP_AN_MSB (0x80)
|
||
|
|
#define NV_SOR_TMDS_HDCP_AN_LSB (0x81)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CN_MSB (0x82)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CN_LSB (0x83)
|
||
|
|
#define NV_SOR_TMDS_HDCP_AKSV_MSB (0x84)
|
||
|
|
#define NV_SOR_TMDS_HDCP_AKSV_LSB (0x85)
|
||
|
|
#define NV_SOR_TMDS_HDCP_BKSV_MSB (0x86)
|
||
|
|
#define REPEATER (1 << 31)
|
||
|
|
#define NV_SOR_TMDS_HDCP_BKSV_LSB (0x87)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CKSV_MSB (0x88)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CKSV_LSB (0x89)
|
||
|
|
#define NV_SOR_TMDS_HDCP_DKSV_MSB (0x8a)
|
||
|
|
#define NV_SOR_TMDS_HDCP_DKSV_LSB (0x8b)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CTRL (0x8c)
|
||
|
|
#define HDCP_RUN_YES (1 << 0)
|
||
|
|
#define CRYPT_ENABLED (1 << 1)
|
||
|
|
#define ONEONE_ENABLED (1 << 3)
|
||
|
|
#define AN_VALID (1 << 8)
|
||
|
|
#define R0_VALID (1 << 9)
|
||
|
|
#define SPRIME_VALID (1 << 10)
|
||
|
|
#define MPRIME_VALID (1 << 11)
|
||
|
|
#define SROM_ERR (1 << 13)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CMODE (0x8d)
|
||
|
|
#define TMDS0_LINK0 (1 << 4)
|
||
|
|
#define READ_S (1 << 0)
|
||
|
|
#define READ_M (2 << 0)
|
||
|
|
#define NV_SOR_TMDS_HDCP_MPRIME_MSB (0x8e)
|
||
|
|
#define NV_SOR_TMDS_HDCP_MPRIME_LSB (0x8f)
|
||
|
|
#define NV_SOR_TMDS_HDCP_SPRIME_MSB (0x90)
|
||
|
|
#define STATUS_CS (1 << 6)
|
||
|
|
#define NV_SOR_TMDS_HDCP_SPRIME_LSB2 (0x91)
|
||
|
|
#define NV_SOR_TMDS_HDCP_SPRIME_LSB1 (0x92)
|
||
|
|
#define NV_SOR_TMDS_HDCP_RI (0x93)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CS_MSB (0x94)
|
||
|
|
#define NV_SOR_TMDS_HDCP_CS_LSB (0x95)
|
||
|
|
|
||
|
|
#define NV_SOR_KEY_CTRL (0xea)
|
||
|
|
#define LOCAL_KEYS (1 << 0)
|
||
|
|
#define AUTOINC (1 << 1)
|
||
|
|
#define WRITE16 (1 << 4)
|
||
|
|
#define PKEY_RELOAD_TRIGGER (1 << 5)
|
||
|
|
#define PKEY_LOADED (1 << 6)
|
||
|
|
|
||
|
|
#define NV_SOR_KEY_DEBUG0 0xeb
|
||
|
|
#define NV_SOR_KEY_DEBUG1 0xec
|
||
|
|
#define NV_SOR_KEY_DEBUG2 0xed
|
||
|
|
#define NV_SOR_KEY_HDCP_KEY_0 0xee
|
||
|
|
#define NV_SOR_KEY_HDCP_KEY_1 0xef
|
||
|
|
#define NV_SOR_KEY_HDCP_KEY_2 0xf0
|
||
|
|
#define NV_SOR_KEY_HDCP_KEY_3 0xf1
|
||
|
|
#define NV_SOR_KEY_HDCP_KEY_TRIG 0xf2
|
||
|
|
#define LOAD_HDCP_KEY (1 << 8)
|
||
|
|
#define NV_SOR_KEY_SKEY_INDEX 0xf3
|
||
|
|
#define NV_PDISP_SOR_AUDIO_SPARE0_0 0xfe
|
||
|
|
#define HDMI_AUDIO_HBR_ENABLE_SHIFT 27
|
||
|
|
|
||
|
|
#define NV_SOR_HDMI_CTRL_REKEY_DEFAULT 58
|
||
|
|
|
||
|
|
#endif
|