143 lines
4.1 KiB
C
143 lines
4.1 KiB
C
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/*
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* Tegra flcn common Module Support
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*
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* Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVHOST_FLCN_H__
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#define __NVHOST_FLCN_H__
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#include <linux/types.h>
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#include <linux/firmware.h>
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#include <linux/platform_device.h>
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struct ucode_bin_header_v1_flcn {
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u32 bin_magic; /* 0x10de */
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u32 bin_ver; /* cya, versioning of bin format (1) */
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u32 bin_size; /* entire image size including this header */
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u32 os_bin_header_offset;
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u32 os_bin_data_offset;
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u32 os_bin_size;
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u32 fce_bin_header_offset;
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u32 fce_bin_data_offset;
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u32 fce_bin_size;
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u32 bin_ver_tag;
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};
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struct ucode_os_header_v1_flcn {
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u32 os_code_offset;
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u32 os_code_size;
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u32 os_data_offset;
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u32 os_data_size;
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u32 num_apps;
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};
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struct ucode_fce_header_v1_flcn {
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u32 fce_ucode_offset;
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u32 fce_ucode_buffer_size;
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u32 fce_ucode_size;
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};
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struct ucode_v1_flcn {
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struct ucode_bin_header_v1_flcn *bin_header;
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struct ucode_os_header_v1_flcn *os_header;
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struct ucode_fce_header_v1_flcn *fce_header;
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bool valid;
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};
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struct flcn_os_image {
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u32 bin_magic;
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u32 reserved_offset;
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u32 bin_data_offset;
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u32 data_offset;
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u32 data_size;
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u32 code_size;
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u32 code_offset;
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u32 size;
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u32 bin_ver_tag;
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};
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struct flcn {
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bool valid;
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size_t size;
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bool is_booted;
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struct flcn_os_image os;
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struct flcn_os_image fce;
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dma_addr_t dma_addr;
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u32 *mapped;
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dma_addr_t fce_dma_addr;
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u32 *fce_mapped;
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};
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static inline struct flcn *get_flcn(struct platform_device *dev)
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{
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return (struct flcn *)nvhost_get_falcon_data(dev);
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}
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static inline void set_flcn(struct platform_device *dev, struct flcn *flcn)
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{
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nvhost_set_falcon_data(dev, flcn);
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}
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int flcn_setup_ucode_image(struct platform_device *dev,
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struct flcn *v,
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const struct firmware *ucode_fw,
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struct ucode_v1_flcn *ucode);
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int nvhost_vic_prepare_poweroff(struct platform_device *);
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int nvhost_flcn_finalize_poweron(struct platform_device *);
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int nvhost_vic_finalize_poweron(struct platform_device *);
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int nvhost_vic_init_context(struct platform_device *pdev,
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struct nvhost_cdma *cdma);
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void flcn_enable_timestamps(struct platform_device *pdev,
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struct nvhost_cdma *cdma,
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dma_addr_t timestamp_addr);
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int nvhost_flcn_prepare_poweroff(struct platform_device *);
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int nvhost_flcn_common_isr(struct platform_device *);
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int nvhost_vic_aggregate_constraints(struct platform_device *dev,
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int clk_index,
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unsigned long floor_rate,
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unsigned long pixelrate,
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unsigned long bw_constraint);
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int nvhost_flcn_wait_mem_scrubbing(struct platform_device *dev);
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int flcn_intr_init(struct platform_device *pdev);
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int flcn_reload_fw(struct platform_device *pdev);
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int nvhost_flcn_load_image(struct platform_device *pdev,
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dma_addr_t dma_addr,
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struct flcn_os_image *os,
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u32 mem_offset);
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int nvhost_flcn_start(struct platform_device *pdev, u32 bootvec);
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void nvhost_flcn_ctxtsw_init(struct platform_device *pdev);
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void nvhost_flcn_irq_dest_set(struct platform_device *pdev);
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void nvhost_flcn_irq_mask_set(struct platform_device *pdev);
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/* hack, get these from elsewhere */
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#define NVA0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID (0x00000200)
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#define NVA0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_SIZE (0x0000071C)
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#define NVA0B6_VIDEO_COMPOSITOR_SET_FCE_UCODE_OFFSET (0x0000072C)
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#define FLCN_UCLASS_METHOD_ADDR_TSP 0xC8
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#define VIC_UCLASS_METHOD_OFFSET 0x10
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#define VIC_UCLASS_METHOD_DATA 0x11
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#define FLCN_UCLASS_METHOD_OFFSET 0x10
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#define FLCN_UCLASS_METHOD_DATA 0x11
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#define NVHOST_ENCODE_FLCN_VER(maj, min) \
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((((maj) & 0xff) << 8) | ((min) & 0xff))
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#endif /* __NVHOST_FLCN_H__ */
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