430 lines
12 KiB
C
430 lines
12 KiB
C
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/*
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* drivers/video/tegra/host/host1x/host1x_intr.c
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*
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* Tegra Graphics Host Interrupt Management
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2010-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include "nvhost_ktime.h"
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#include "nvhost_intr.h"
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#include "dev.h"
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/* Spacing between sync registers */
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#define REGISTER_STRIDE 4
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static void t20_intr_syncpt_intr_ack(struct nvhost_intr_syncpt *syncpt,
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bool disable_intr);
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static void t20_intr_enable_syncpt_intr(struct nvhost_intr *intr, u32 id);
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static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
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u32 id, u32 thresh);
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static irqreturn_t syncpt_thresh_cascade_isr(int irq, void *dev_id)
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{
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struct nvhost_master *dev = dev_id;
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struct nvhost_intr *intr = &dev->intr;
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unsigned long reg;
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int i, id;
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struct nvhost_timespec isr_recv;
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nvhost_ktime_get_ts(&isr_recv);
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for (i = 0; i < DIV_ROUND_UP(nvhost_syncpt_nb_hw_pts(&dev->syncpt), 32);
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i++) {
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reg = host1x_sync_readl(dev,
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host1x_sync_syncpt_thresh_cpu0_int_status_r() +
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i * REGISTER_STRIDE);
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for_each_set_bit(id, ®, 32) {
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struct nvhost_intr_syncpt *sp;
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int sp_id = i * 32 + id;
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int graphics_host_sp =
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nvhost_syncpt_graphics_host_sp(&dev->syncpt);
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if (unlikely(!nvhost_syncpt_is_valid_hw_pt(&dev->syncpt,
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sp_id))) {
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dev_err(&dev->dev->dev, "%s(): syncpoint id %d is beyond the number of syncpoints (%d)\n",
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__func__, sp_id,
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nvhost_syncpt_nb_hw_pts(&dev->syncpt));
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goto out;
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}
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sp = intr->syncpt + sp_id;
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sp->isr_recv = isr_recv;
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/* handle graphics host syncpoint increments
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* immediately
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*/
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if (sp_id == graphics_host_sp) {
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dev_warn(&dev->dev->dev, "%s(): syncpoint id %d incremented\n",
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__func__, graphics_host_sp);
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nvhost_syncpt_patch_check(&dev->syncpt);
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t20_intr_syncpt_intr_ack(sp, false);
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} else {
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t20_intr_syncpt_intr_ack(sp, true);
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nvhost_syncpt_thresh_fn(sp);
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}
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}
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}
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out:
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return IRQ_HANDLED;
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}
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static void t20_intr_set_host_clocks_per_usec(struct nvhost_intr *intr, u32 cpm)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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/* write microsecond clock register */
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host1x_sync_writel(dev, host1x_sync_usec_clk_r(), cpm);
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/* set the ip_busy_timeout */
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host1x_sync_writel(dev,
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host1x_sync_ip_busy_timeout_r(), cpm * 500000);
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}
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static void t20_intr_set_syncpt_threshold(struct nvhost_intr *intr,
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u32 id, u32 thresh)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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host1x_sync_writel(dev, (host1x_sync_syncpt_int_thresh_0_r() +
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id * REGISTER_STRIDE), thresh);
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}
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static void t20_intr_enable_syncpt_intr(struct nvhost_intr *intr, u32 id)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_int_enable_cpu0_r() +
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bit_word(id) * REGISTER_STRIDE, bit_mask(id));
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}
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static void t20_intr_disable_syncpt_intr(struct nvhost_intr *intr, u32 id)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_int_disable_r() +
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bit_word(id) * REGISTER_STRIDE, bit_mask(id));
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/* clear status for both cpu's */
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_cpu0_int_status_r() +
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bit_word(id) * REGISTER_STRIDE, bit_mask(id));
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}
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static void t20_intr_disable_all_syncpt_intrs(struct nvhost_intr *intr)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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u32 reg;
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for (reg = 0; reg < bit_word(nvhost_syncpt_nb_hw_pts(&dev->syncpt))
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* REGISTER_STRIDE; reg += REGISTER_STRIDE) {
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/* disable interrupts for both cpu's */
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_int_disable_r() +
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reg, 0xffffffffu);
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/* clear status for both cpu's */
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_cpu0_int_status_r() + reg,
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0xffffffffu);
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}
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}
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/*
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* Check if some client erroneously added extra increments and we have
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* MIN > MAX situation
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* If yes, set MIN == MAX explicitly
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*/
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static void t20_intr_handle_extra_increments(struct nvhost_master *dev,
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unsigned int id)
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{
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u32 min, max;
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if (nvhost_syncpt_client_managed(&dev->syncpt, id))
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return;
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min = nvhost_syncpt_update_min(&dev->syncpt, id);
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max = nvhost_syncpt_read_maxval(dev->dev, id);
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if ((s32)(min - max) > 0)
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nvhost_syncpt_set_min_eq_max(&dev->syncpt, id);
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}
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/*
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* Acknowledge that the syncpoint interrupt is handled. If disable_intr is set,
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* the syncpoint interrupt is also disabled.
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*/
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static void t20_intr_syncpt_intr_ack(struct nvhost_intr_syncpt *syncpt,
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bool disable_intr)
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{
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unsigned int id = syncpt->id;
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struct nvhost_intr *intr = intr_syncpt_to_intr(syncpt);
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struct nvhost_master *dev = intr_to_dev(intr);
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u32 reg = bit_word(id) * REGISTER_STRIDE;
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if (disable_intr)
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_int_disable_r() + reg,
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bit_mask(id));
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t20_intr_handle_extra_increments(dev, id);
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host1x_sync_writel(dev,
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host1x_sync_syncpt_thresh_cpu0_int_status_r() + reg,
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bit_mask(id));
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}
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/**
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* Host general interrupt service function
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* Handles read / write failures
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*/
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static irqreturn_t t20_intr_host1x_isr(int irq, void *dev_id)
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{
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struct nvhost_intr *intr = dev_id;
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struct nvhost_master *dev = intr_to_dev(intr);
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unsigned long stat;
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u32 ext_stat;
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u32 addr;
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unsigned long intstat;
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int i;
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intstat = host1x_sync_readl(dev, host1x_sync_intstatus_r());
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intr->intstatus = intstat;
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/* Handle host1x interrupt in ISR */
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stat = host1x_sync_readl(dev, host1x_sync_hintstatus_r());
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ext_stat = host1x_sync_readl(dev, host1x_sync_hintstatus_ext_r());
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for_each_set_bit(i, &stat, 32) {
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if (intr->host_isr[i])
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intr->host_isr[i](stat, intr->host_isr_priv[i]);
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}
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if (host1x_sync_hintstatus_ext_ip_read_int_v(ext_stat)) {
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addr = host1x_sync_readl(dev,
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host1x_sync_ip_read_timeout_addr_r());
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pr_err("Host read timeout at address %x\n", addr);
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}
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if (host1x_sync_hintstatus_ext_ip_write_int_v(ext_stat)) {
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addr = host1x_sync_readl(dev,
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host1x_sync_ip_write_timeout_addr_r());
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pr_err("Host write timeout at address %x\n", addr);
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}
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host1x_sync_writel(dev, host1x_sync_hintstatus_ext_r(), ext_stat);
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host1x_sync_writel(dev, host1x_sync_hintstatus_r(), stat);
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host1x_sync_writel(dev, host1x_sync_intstatus_r(), intstat);
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return IRQ_HANDLED;
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}
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static int intr_debug_dump(struct nvhost_intr *intr, struct output *o)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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int i;
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nvhost_debug_output(o, "\n---- host general irq ----\n\n");
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nvhost_debug_output(o, "sync_hintmask_ext = 0x%08x\n",
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host1x_sync_readl(dev, host1x_sync_hintmask_ext_r()));
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nvhost_debug_output(o, "sync_hintmask = 0x%08x\n",
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host1x_sync_readl(dev, host1x_sync_hintmask_r()));
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nvhost_debug_output(o, "sync_intc0mask = 0x%08x\n",
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host1x_sync_readl(dev, host1x_sync_intc0mask_r()));
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nvhost_debug_output(o, "sync_intmask = 0x%08x\n",
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host1x_sync_readl(dev, host1x_sync_intmask_r()));
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nvhost_debug_output(o, "\n---- host syncpt irq mask ----\n\n");
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for (i = 0; i < DIV_ROUND_UP(nvhost_syncpt_nb_hw_pts(&dev->syncpt), 16);
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i++)
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nvhost_debug_output(o, "syncpt_thresh_int_mask(%d) = 0x%08x\n",
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i, host1x_sync_readl(dev,
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host1x_sync_syncpt_thresh_int_mask_r() +
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i * REGISTER_STRIDE));
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nvhost_debug_output(o, "\n---- host syncpt irq status ----\n\n");
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for (i = 0; i < DIV_ROUND_UP(nvhost_syncpt_nb_hw_pts(&dev->syncpt), 32);
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i++)
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nvhost_debug_output(o, "syncpt_thresh_cpu0_int_status(%d) = 0x%08x\n",
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i, host1x_sync_readl(dev,
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host1x_sync_syncpt_thresh_cpu0_int_status_r() +
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i * REGISTER_STRIDE));
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nvhost_debug_output(o, "\n---- host syncpt thresh ----\n\n");
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for (i = 0; i < nvhost_syncpt_nb_hw_pts(&dev->syncpt); i++) {
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u32 reg = host1x_sync_readl(dev,
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host1x_sync_syncpt_thresh_int_mask_r() +
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bit_word(i * 2) * REGISTER_STRIDE);
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if (!(reg & bit_mask(i * 2)))
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continue;
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nvhost_debug_output(o, "syncpt_int_thresh_thresh_0(%d) = %u\n",
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i, host1x_sync_readl(dev,
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host1x_sync_syncpt_int_thresh_0_r() +
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i * REGISTER_STRIDE));
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}
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return 0;
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}
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static void intr_enable_host_irq(struct nvhost_intr *intr, int irq)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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long val;
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val = host1x_sync_readl(dev, host1x_sync_hintmask_r());
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val |= BIT(irq);
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host1x_sync_writel(dev, host1x_sync_hintmask_r(), val);
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}
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static void intr_disable_host_irq(struct nvhost_intr *intr, int irq)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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long val;
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val = host1x_sync_readl(dev, host1x_sync_hintmask_r());
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val &= ~BIT(irq);
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host1x_sync_writel(dev, host1x_sync_hintmask_r(), val);
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}
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static void intr_enable_module_intr(struct nvhost_intr *intr, int irq)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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long val;
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val = host1x_sync_readl(dev, host1x_sync_intc0mask_r());
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val |= BIT(irq);
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host1x_sync_writel(dev, host1x_sync_intc0mask_r(), val);
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}
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static void intr_disable_module_intr(struct nvhost_intr *intr, int irq)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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long val;
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val = host1x_sync_readl(dev, host1x_sync_intc0mask_r());
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val &= ~BIT(irq);
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host1x_sync_writel(dev, host1x_sync_intc0mask_r(), val);
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}
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static void t20_intr_resume(struct nvhost_intr *intr)
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{
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struct nvhost_master *dev = intr_to_dev(intr);
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u32 val;
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/* increase the auto-ack timout to the maximum value. 2d will hang
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* otherwise on ap20.
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*/
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host1x_sync_writel(dev, host1x_sync_ctxsw_timeout_cfg_r(), 0xff);
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/* enable graphics host syncpoint interrupt */
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t20_intr_set_syncpt_threshold(intr,
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||
|
|
nvhost_syncpt_graphics_host_sp(&dev->syncpt),
|
||
|
|
1);
|
||
|
|
t20_intr_enable_syncpt_intr(intr,
|
||
|
|
nvhost_syncpt_graphics_host_sp(&dev->syncpt));
|
||
|
|
|
||
|
|
/* enable extra interrupt sources IP_READ_INT and IP_WRITE_INT */
|
||
|
|
host1x_sync_writel(dev, host1x_sync_hintmask_ext_r(),
|
||
|
|
BIT(30) | BIT(31));
|
||
|
|
|
||
|
|
/* enable extra interrupt sources */
|
||
|
|
val = host1x_sync_readl(dev, host1x_sync_hintmask_r());
|
||
|
|
val |= BIT(31);
|
||
|
|
host1x_sync_writel(dev, host1x_sync_hintmask_r(), val);
|
||
|
|
|
||
|
|
/* enable host module interrupt to CPU0 */
|
||
|
|
host1x_sync_writel(dev, host1x_sync_intc0mask_r(), BIT(0));
|
||
|
|
|
||
|
|
/* master enable for general (not syncpt) host interrupts */
|
||
|
|
host1x_sync_writel(dev, host1x_sync_intmask_r(), BIT(0));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void t20_intr_suspend(struct nvhost_intr *intr)
|
||
|
|
{
|
||
|
|
struct nvhost_master *dev = intr_to_dev(intr);
|
||
|
|
|
||
|
|
/* master disable for general (not syncpt) host interrupts */
|
||
|
|
host1x_sync_writel(dev, host1x_sync_intmask_r(), 0);
|
||
|
|
|
||
|
|
/* disable graphics host syncpoint interrupt */
|
||
|
|
t20_intr_disable_syncpt_intr(intr,
|
||
|
|
nvhost_syncpt_graphics_host_sp(&dev->syncpt));
|
||
|
|
}
|
||
|
|
|
||
|
|
static int t20_intr_init(struct nvhost_intr *intr)
|
||
|
|
{
|
||
|
|
struct nvhost_master *dev = intr_to_dev(intr);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
intr_op().disable_all_syncpt_intrs(intr);
|
||
|
|
|
||
|
|
err = request_threaded_irq(intr->syncpt_irq, NULL,
|
||
|
|
syncpt_thresh_cascade_isr,
|
||
|
|
IRQF_ONESHOT, "host_syncpt", dev);
|
||
|
|
if (err)
|
||
|
|
return err;
|
||
|
|
|
||
|
|
/* master disable for general (not syncpt) host interrupts */
|
||
|
|
host1x_sync_writel(dev, host1x_sync_intmask_r(), 0);
|
||
|
|
|
||
|
|
/* clear status & extstatus */
|
||
|
|
host1x_sync_writel(dev, host1x_sync_hintstatus_ext_r(),
|
||
|
|
0xfffffffful);
|
||
|
|
host1x_sync_writel(dev, host1x_sync_hintstatus_r(),
|
||
|
|
0xfffffffful);
|
||
|
|
|
||
|
|
err = request_threaded_irq(intr->general_irq, NULL,
|
||
|
|
t20_intr_host1x_isr,
|
||
|
|
IRQF_ONESHOT, "host_status", intr);
|
||
|
|
if (err) {
|
||
|
|
free_irq(intr->syncpt_irq, dev);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void t20_intr_deinit(struct nvhost_intr *intr)
|
||
|
|
{
|
||
|
|
struct nvhost_master *dev = intr_to_dev(intr);
|
||
|
|
|
||
|
|
free_irq(intr->general_irq, intr);
|
||
|
|
free_irq(intr->syncpt_irq, dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvhost_intr_ops host1x_intr_ops = {
|
||
|
|
.init = t20_intr_init,
|
||
|
|
.deinit = t20_intr_deinit,
|
||
|
|
.resume = t20_intr_resume,
|
||
|
|
.suspend = t20_intr_suspend,
|
||
|
|
.set_host_clocks_per_usec = t20_intr_set_host_clocks_per_usec,
|
||
|
|
.set_syncpt_threshold = t20_intr_set_syncpt_threshold,
|
||
|
|
.enable_syncpt_intr = t20_intr_enable_syncpt_intr,
|
||
|
|
.disable_syncpt_intr = t20_intr_disable_syncpt_intr,
|
||
|
|
.disable_all_syncpt_intrs = t20_intr_disable_all_syncpt_intrs,
|
||
|
|
.debug_dump = intr_debug_dump,
|
||
|
|
.enable_host_irq = intr_enable_host_irq,
|
||
|
|
.disable_host_irq = intr_disable_host_irq,
|
||
|
|
.enable_module_intr = intr_enable_module_intr,
|
||
|
|
.disable_module_intr = intr_disable_module_intr,
|
||
|
|
};
|