110 lines
3.0 KiB
C
110 lines
3.0 KiB
C
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/*
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* PVA ISR code for T194
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*
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* Copyright (c) 2016-2018, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include "bus_client.h"
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#include "pva_regs.h"
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#include "dev.h"
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#include "pva.h"
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static irqreturn_t pva_isr(int irq, void *dev_id)
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{
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struct pva *pva = dev_id;
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struct platform_device *pdev = pva->pdev;
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u32 checkpoint = host1x_readl(pdev, cfg_ccq_status8_r());
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u32 status7 = pva_read_mailbox(pdev, PVA_MBOX_ISR);
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u32 status5 = pva_read_mailbox(pdev, PVA_MBOX_AISR);
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u32 lic_int_status = host1x_readl(pdev, sec_lic_intr_status_r());
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bool recover = false;
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if (status5 & PVA_AISR_INT_PENDING) {
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nvhost_dbg_info("PVA AISR (%x)", status5);
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/* For now, just log the errors */
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if (status5 & PVA_AISR_TASK_ERROR)
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nvhost_warn(&pdev->dev, "PVA AISR: PVA_AISR_TASK_ERROR");
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if (status5 & PVA_AISR_THRESHOLD_EXCEEDED)
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nvhost_warn(&pdev->dev, "PVA AISR: PVA_AISR_THRESHOLD_EXCEEDED");
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if (status5 & PVA_AISR_LOGGING_OVERFLOW)
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nvhost_warn(&pdev->dev, "PVA AISR: PVA_AISR_LOGGING_OVERFLOW");
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if (status5 & PVA_AISR_PRINTF_OVERFLOW)
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nvhost_warn(&pdev->dev, "PVA AISR: PVA_AISR_PRINTF_OVERFLOW");
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if (status5 & PVA_AISR_CRASH_LOG)
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nvhost_warn(&pdev->dev, "PVA AISR: PVA_AISR_CRASH_LOG");
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if (status5 & PVA_AISR_ABORT) {
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nvhost_warn(&pdev->dev, "PVA AISR: PVA_AISR_ABORT");
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nvhost_warn(&pdev->dev, "Checkpoint value: 0x%08x",
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checkpoint);
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recover = true;
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}
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pva_write_mailbox(pdev, PVA_MBOX_AISR, 0x0);
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}
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if (status7 & PVA_INT_PENDING) {
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nvhost_dbg_info("PVA ISR (%x)", status7);
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pva_mailbox_isr(pva);
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}
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/* Check for watchdog timer interrupt */
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if (lic_int_status & sec_lic_intr_enable_wdt_f(SEC_LIC_INTR_WDT)) {
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nvhost_warn(&pdev->dev, "WatchDog Timer");
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recover = true;
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}
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/* Copy trace points to ftrace buffer */
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pva_trace_copy_to_ftrace(pva);
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if (recover)
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pva_abort(pva);
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return IRQ_HANDLED;
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}
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int pva_register_isr(struct platform_device *dev)
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{
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struct nvhost_device_data *pdata = platform_get_drvdata(dev);
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struct pva *pva = pdata->private_data;
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int err;
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pva->irq = platform_get_irq(dev, 0);
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if (pva->irq <= 0) {
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dev_err(&dev->dev, "no irq\n");
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err = -ENOENT;
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goto isr_err;
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}
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err = request_threaded_irq(pva->irq, NULL, pva_isr,
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IRQF_ONESHOT, "pva-isr", pva);
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if (err) {
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pr_err("%s: request_irq(%d) failed(%d)\n", __func__,
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pva->irq, err);
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goto isr_err;
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}
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disable_irq(pva->irq);
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isr_err:
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return err;
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}
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