113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
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/*
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* PVA uCode Self Test
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/nvhost.h>
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#include <linux/delay.h>
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#include <linux/iommu.h>
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#include <linux/dma-mapping.h>
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#include "dev.h"
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#include "pva.h"
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/* Defines for self test-mode in ucode */
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#define PVA_MBOX_VAL_TESTS_DONE 0x57800000
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#define PVA_SELF_TESTMODE_START_ADDR 0x90000000
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#define PVA_SELF_TESTMODE_ADDR_SIZE 0x00800000
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int pva_run_ucode_selftest(struct platform_device *pdev)
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{
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struct nvhost_device_data *pdata = platform_get_drvdata(pdev);
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struct pva *pva = pdata->private_data;
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int err = 0;
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u32 reg_status;
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u32 ucode_mode;
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void *selftest_cpuaddr;
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dma_addr_t base_iova = PVA_SELF_TESTMODE_START_ADDR;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)
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struct dma_attrs attrs;
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init_dma_attrs(&attrs);
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#else
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unsigned long attrs = 0;
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#endif
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/* Map static memory for self test mode */
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nvhost_dbg_info("uCode TESTMODE Enabled");
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dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, __DMA_ATTR(attrs));
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dma_set_attr(DMA_ATTR_SKIP_IOVA_GAP, __DMA_ATTR(attrs));
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selftest_cpuaddr = dma_alloc_at_attrs(&pdev->dev,
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PVA_SELF_TESTMODE_ADDR_SIZE, &base_iova,
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GFP_KERNEL|__GFP_ZERO, __DMA_ATTR(attrs));
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if (!selftest_cpuaddr) {
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dev_warn(&pdev->dev, "Failed to get Selftest Static memory\n");
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err = -ENOMEM;
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goto err_selftest;
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}
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pva->mailbox_status = PVA_MBOX_STATUS_WFI;
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host1x_writel(pdev, hsp_ss0_set_r(), PVA_TEST_RUN);
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/* Wait till we get a AISR_ABORT interrupt */
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err = pva_mailbox_wait_event(pva, 60000);
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if (err)
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goto wait_timeout;
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ucode_mode = host1x_readl(pdev, hsp_ss0_state_r());
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/*Check whether ucode halted */
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if ((ucode_mode & PVA_HALTED) == 0) {
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nvhost_dbg_info("uCode SELFTEST Failed to Halt");
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err = -EINVAL;
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goto err_selftest;
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}
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reg_status = pva_read_mailbox(pdev, PVA_MBOX_ISR);
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/* check test passed bit set and test status done*/
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if ((ucode_mode & PVA_TESTS_PASSED) &&
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(reg_status == PVA_MBOX_VAL_TESTS_DONE))
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nvhost_dbg_info("uCode SELFTEST Passed");
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else if (ucode_mode & PVA_TESTS_FAILED)
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nvhost_dbg_info("uCode SELFTEST Failed");
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else
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nvhost_dbg_info("uCode SELFTEST UnKnown State");
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/* Get CCQ8 register value */
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reg_status = host1x_readl(pdev, cfg_ccq_status8_r());
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nvhost_dbg_info("Major 0x%x, Minor 0x%x, Flags 0x%x, Trace Sequence 0x%x \n",
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(reg_status & 0xFF000000) >> 24,
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(reg_status & 0x00FF0000) >> 16,
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(reg_status & 0xFF00) >> 8,
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(reg_status & 0xFF));
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wait_timeout:
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err_selftest:
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if (selftest_cpuaddr)
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dma_free_attrs(&pdev->dev,
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PVA_SELF_TESTMODE_ADDR_SIZE, selftest_cpuaddr,
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PVA_SELF_TESTMODE_START_ADDR, __DMA_ATTR(attrs));
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return err;
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}
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