116 lines
3.9 KiB
C
116 lines
3.9 KiB
C
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/*
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* include/linux/platform/reset.h
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*
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* CPU reset dispatcher.
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*
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* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_TEGRA_RESET_H
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#define __MACH_TEGRA_RESET_H
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#define TEGRA_RESET_MASK_PRESENT 0
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#define TEGRA_RESET_MASK_LP1 1
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#define TEGRA_RESET_MASK_LP2 2
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#define TEGRA_RESET_STARTUP_SECONDARY 3
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#define TEGRA_RESET_STARTUP_LP2 4
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#define TEGRA_RESET_STARTUP_LP1 5
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#define TEGRA_RESET_C0_L2_TAG_LATENCY 6
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#define TEGRA_RESET_C0_L2_DATA_LATENCY 7
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#define TEGRA_RESET_C1_L2_TAG_LATENCY 8
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#define TEGRA_RESET_C1_L2_DATA_LATENCY 9
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#define TEGRA_RESET_MASK_MC_CLK 10
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#define TEGRA_RESET_SECURE_FW_PRESENT 11
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#define TEGRA_RESET_DATA_SIZE 12
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#ifdef CONFIG_ARM64
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#define RESET_DATA(x) ((TEGRA_RESET_##x)*8)
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#else
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#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
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#endif
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#ifndef __ASSEMBLY__
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#include <linux/cpumask.h>
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extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra_cpu_reset_handler_end(void);
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void tegra_secondary_startup(void);
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#ifdef CONFIG_PM_SLEEP
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#define tegra_cpu_lp1_mask ((unsigned long *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
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(ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_mc_clk_mask ((unsigned long *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_MC_CLK] - \
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(ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_cpu_reset_handler_ptr ((u32 *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)__tegra_cpu_reset_handler_data - \
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(ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_cpu_lp2_mask ((cpumask_t *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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(ulong)__tegra_cpu_reset_handler_start))))
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#endif
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#define tegra_cpu_c0_l2_tag_latency \
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__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_TAG_LATENCY]
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#define tegra_cpu_c0_l2_tag_latency_iram \
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((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_TAG_LATENCY] \
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- (ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_cpu_c0_l2_data_latency \
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__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_DATA_LATENCY]
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#define tegra_cpu_c0_l2_data_latency_iram \
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((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_DATA_LATENCY] \
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- (ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_cpu_c1_l2_tag_latency \
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__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_TAG_LATENCY]
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#define tegra_cpu_c1_l2_tag_latency_iram \
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((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_TAG_LATENCY] \
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- (ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_cpu_c1_l2_data_latency \
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__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_DATA_LATENCY]
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#define tegra_cpu_c1_l2_data_latency_iram \
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((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
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((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_DATA_LATENCY] \
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- (ulong)__tegra_cpu_reset_handler_start))))
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#define tegra_cpu_reset_handler_offset \
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((ulong)__tegra_cpu_reset_handler - \
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(ulong)__tegra_cpu_reset_handler_start)
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#define tegra_cpu_reset_handler_size \
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(__tegra_cpu_reset_handler_end - \
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__tegra_cpu_reset_handler_start)
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#ifdef CONFIG_PM_SLEEP
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void tegra_cpu_reset_handler_save(void);
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void tegra_cpu_reset_handler_restore(void);
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#endif
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#endif
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#endif
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