122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
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/*
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* Tegra Graphics Host VI
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*
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVHOST_VI_H__
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#define __NVHOST_VI_H__
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#include <linux/tegra-powergate.h>
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#include <linux/clk/tegra.h>
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#include <media/mc_common.h>
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#include "chip_support.h"
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#define VI_CFG_INTERRUPT_MASK_0 0x8c
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#define VI_CFG_INTERRUPT_STATUS_0 0x98
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#define CSI_CSI_PIXEL_PARSER_A_INTERRUPT_MASK_0 0x850
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#define CSI_CSI_PIXEL_PARSER_A_STATUS_0 0x854
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#define PPA_FIFO_OVRF (1 << 5)
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#define CSI_CSI_PIXEL_PARSER_B_INTERRUPT_MASK_0 0x884
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#define CSI_CSI_PIXEL_PARSER_B_STATUS_0 0x888
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#define PPB_FIFO_OVRF (1 << 5)
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#define VI_CSI_0_ERROR_STATUS 0x184
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#define VI_CSI_1_ERROR_STATUS 0x284
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#define VI_CSI_0_WD_CTRL 0x18c
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#define VI_CSI_1_WD_CTRL 0x28c
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#define VI_CSI_0_ERROR_INT_MASK_0 0x188
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#define VI_CSI_1_ERROR_INT_MASK_0 0x288
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#ifdef TEGRA_21X_OR_HIGHER_CONFIG
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#define VI_CSI_2_ERROR_STATUS 0x384
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#define VI_CSI_3_ERROR_STATUS 0x484
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#define VI_CSI_4_ERROR_STATUS 0x584
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#define VI_CSI_5_ERROR_STATUS 0x684
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#define VI_CSI_2_WD_CTRL 0x38c
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#define VI_CSI_3_WD_CTRL 0x48c
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#define VI_CSI_4_WD_CTRL 0x58c
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#define VI_CSI_5_WD_CTRL 0x68c
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#define VI_CSI_2_ERROR_INT_MASK_0 0x388
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#define VI_CSI_3_ERROR_INT_MASK_0 0x488
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#define VI_CSI_4_ERROR_INT_MASK_0 0x588
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#define VI_CSI_5_ERROR_INT_MASK_0 0x688
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#define CSI1_CSI_PIXEL_PARSER_A_INTERRUPT_MASK_0 0x1050
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#define CSI1_CSI_PIXEL_PARSER_A_STATUS_0 0x1054
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#define CSI1_CSI_PIXEL_PARSER_B_INTERRUPT_MASK_0 0x1084
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#define CSI1_CSI_PIXEL_PARSER_B_STATUS_0 0x1088
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#define CSI2_CSI_PIXEL_PARSER_A_INTERRUPT_MASK_0 0x1850
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#define CSI2_CSI_PIXEL_PARSER_A_STATUS_0 0x1854
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#define CSI2_CSI_PIXEL_PARSER_B_INTERRUPT_MASK_0 0x1884
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#define CSI2_CSI_PIXEL_PARSER_B_STATUS_0 0x1888
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#define NUM_VI_WATCHDOG 6
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#else
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#define NUM_VI_WATCHDOG 2
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#endif
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typedef void (*callback)(void *);
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struct tegra_vi_stats {
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atomic_t overflow;
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};
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struct tegra_vi_mfi_ctx;
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struct vi {
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struct tegra_camera *camera;
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struct platform_device *ndev;
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struct device *dev;
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struct tegra_vi_data *data;
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struct tegra_mc_vi mc_vi;
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struct tegra_csi_device csi;
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struct regulator *reg;
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struct dentry *debugdir;
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struct tegra_vi_stats vi_out;
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struct work_struct stats_work;
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struct tegra_vi_mfi_ctx *mfi_ctx;
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int vi_irq;
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uint vi_bypass_bw;
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uint max_bw;
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bool master_deinitialized;
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bool tpg_opened;
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bool sensor_opened;
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bool bypass;
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};
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extern const struct file_operations tegra_vi_ctrl_ops;
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int nvhost_vi_prepare_poweroff(struct platform_device *);
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int nvhost_vi_finalize_poweron(struct platform_device *);
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void nvhost_vi_reset_all(struct platform_device *);
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struct vi *tegra_vi_get(void);
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int vi_v4l2_set_la(struct vi *tegra_vi, u32 vi_bypass_bw, bool is_ioctl);
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int tegra_vi_register_mfi_cb(callback cb, void *cb_arg);
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int tegra_vi_unregister_mfi_cb(void);
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bool tegra_vi_has_mfi_callback(void);
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int tegra_vi_mfi_event_notify(struct tegra_vi_mfi_ctx *mfi_ctx, u8 channel);
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int tegra_vi_init_mfi(struct tegra_vi_mfi_ctx **mfi_ctx, u8 num_channels);
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void tegra_vi_deinit_mfi(struct tegra_vi_mfi_ctx **mfi_ctx);
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#endif
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