182 lines
7.9 KiB
C
182 lines
7.9 KiB
C
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/*
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* tegra186_asrc_alt.h - Definitions for Tegra186 ASRC driver
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA186_ASRC_ALT_H__
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#define __TEGRA186_ASRC_ALT_H__
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#define TEGRA186_ASRC_STREAM_STRIDE 0x80
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#define TEGRA186_ASRC_STREAM_MAX 6
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#define TEGRA186_ASRC_STREAM_LIMIT 0x2f0
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/* ASRC stream related offset */
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#define TEGRA186_ASRC_STREAM1_CONFIG 0x0
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#define TEGRA186_ASRC_STREAM1_RATIO_INTEGER_PART 0x4
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#define TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART 0x8
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#define TEGRA186_ASRC_STREAM1_RATIO_LOCK_STATUS 0xc
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#define TEGRA186_ASRC_STREAM1_MUTE_UNMUTE_DURATION 0x10
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#define TEGRA186_ASRC_STREAM1_TX_THRESHOLD 0x14
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#define TEGRA186_ASRC_STREAM1_RX_THRESHOLD 0x18
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#define TEGRA186_ASRC_STREAM1_RATIO_COMP 0x1C
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#define TEGRA186_ASRC_STREAM1_RX_STATUS 0x20
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#define TEGRA186_ASRC_STREAM1_RX_CIF_CTRL 0x24
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#define TEGRA186_ASRC_STREAM1_TX_STATUS 0x2c
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#define TEGRA186_ASRC_STREAM1_TX_CIF_CTRL 0x30
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#define TEGRA186_ASRC_STREAM1_ENABLE 0x38
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#define TEGRA186_ASRC_STREAM1_SOFT_RESET 0x3c
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#define TEGRA186_ASRC_STREAM1_STATUS 0x4c
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#define TEGRA186_ASRC_STREAM1_BUFFER_STATUS 0x50
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#define TEGRA186_ASRC_STREAM1_CONFIG_ERR_TYPE 0x54
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#define TEGRA186_ASRC_STREAM1_STATEBUF_ADDR 0x5c
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#define TEGRA186_ASRC_STREAM1_STATEBUF_CONFIG 0x60
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#define TEGRA186_ASRC_STREAM1_INSAMPLEBUF_ADDR 0x64
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#define TEGRA186_ASRC_STREAM1_INSAMPLEBUF_CONFIG 0x68
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#define TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_ADDR 0x6c
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#define TEGRA186_ASRC_STREAM1_OUTSAMPLEBUF_CONFIG 0x70
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#define TEGRA186_ASRC_STREAM2_RATIO_INTEGER_PART 0x84
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#define TEGRA186_ASRC_STREAM2_RATIO_FRAC_PART 0x88
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#define TEGRA186_ASRC_STREAM3_RATIO_INTEGER_PART 0x104
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#define TEGRA186_ASRC_STREAM3_RATIO_FRAC_PART 0x108
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#define TEGRA186_ASRC_STREAM4_RATIO_INTEGER_PART 0x184
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#define TEGRA186_ASRC_STREAM4_RATIO_FRAC_PART 0x188
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#define TEGRA186_ASRC_STREAM5_RATIO_INTEGER_PART 0x204
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#define TEGRA186_ASRC_STREAM5_RATIO_FRAC_PART 0x208
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#define TEGRA186_ASRC_STREAM6_RATIO_INTEGER_PART 0x284
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#define TEGRA186_ASRC_STREAM6_RATIO_FRAC_PART 0x288
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#define TEGRA186_ASRC_STREAM1_ENABLE 0x38
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#define TEGRA186_ASRC_STREAM2_ENABLE 0xb8
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#define TEGRA186_ASRC_STREAM3_ENABLE 0x138
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#define TEGRA186_ASRC_STREAM4_ENABLE 0x1b8
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#define TEGRA186_ASRC_STREAM5_ENABLE 0x238
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#define TEGRA186_ASRC_STREAM6_ENABLE 0x2b8
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#define TEGRA186_ASRC_STREAM2_CONFIG 0x80
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#define TEGRA186_ASRC_STREAM3_CONFIG 0x100
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#define TEGRA186_ASRC_STREAM4_CONFIG 0x180
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#define TEGRA186_ASRC_STREAM5_CONFIG 0x200
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#define TEGRA186_ASRC_STREAM6_CONFIG 0x280
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#define TEGRA186_ASRC_STREAM2_TX_THRESHOLD 0x94
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#define TEGRA186_ASRC_STREAM3_TX_THRESHOLD 0x114
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#define TEGRA186_ASRC_STREAM4_TX_THRESHOLD 0x194
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#define TEGRA186_ASRC_STREAM5_TX_THRESHOLD 0x214
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#define TEGRA186_ASRC_STREAM6_TX_THRESHOLD 0x294
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#define TEGRA186_ASRC_STREAM2_RX_THRESHOLD 0x98
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#define TEGRA186_ASRC_STREAM3_RX_THRESHOLD 0x118
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#define TEGRA186_ASRC_STREAM4_RX_THRESHOLD 0x198
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#define TEGRA186_ASRC_STREAM5_RX_THRESHOLD 0x218
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#define TEGRA186_ASRC_STREAM6_RX_THRESHOLD 0x298
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/* ASRC UPD related offset */
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#define TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL 0x30c
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#define TEGRA186_ASRC_RATIO_UPD_RX_STATUS 0x310
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/* ASRC Global registers offset */
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#define TEGRA186_ASRC_GLOBAL_ENB 0x2f4
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#define TEGRA186_ASRC_GLOBAL_SOFT_RESET 0x2f8
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#define TEGRA186_ASRC_GLOBAL_CG 0x2fc
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#define TEGRA186_ASRC_GLOBAL_CONFIG 0x300
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#define TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR 0x304
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#define TEGRA186_ASRC_GLOBAL_SCRATCH_CONFIG 0x308
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#define TEGRA186_ASRC_GLOBAL_STATUS 0x314
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#define TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS 0x318
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#define TEGRA186_ASRC_GLOBAL_INT_STATUS 0x324
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#define TEGRA186_ASRC_GLOBAL_INT_MASK 0x328
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#define TEGRA186_ASRC_GLOBAL_INT_SET 0x32c
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#define TEGRA186_ASRC_GLOBAL_INT_CLEAR 0x330
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#define TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG 0x334
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#define TEGRA186_ASRC_GLOBAL_APR_CTRL 0x1000
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#define TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL 0x1004
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#define TEGRA186_ASRC_GLOBAL_DISARM_APR 0x1008
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#define TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL 0x100c
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#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS 0x1010
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#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL 0x1014
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#define TEGRA186_ASRC_CYA 0x1018
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#define TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE 0xaaaa
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#define TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CONFIG 0x00201002
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#define TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CONFIG 0x00201002
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT 31
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
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#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE (0 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)
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#define TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT 0
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#define TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK (1 << TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT)
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#define TEGRA186_ASRC_STREAM_EN_SHIFT 0
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#define TEGRA186_ASRC_STREAM_EN (1 << TEGRA186_ASRC_STREAM_EN_SHIFT)
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#define TEGRA186_ASRC_GLOBAL_EN_SHIFT 0
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#define TEGRA186_ASRC_GLOBAL_EN (1 << TEGRA186_ASRC_GLOBAL_EN_SHIFT)
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#define TEGRA186_ASRC_STREAM_STATEBUF_CONFIG_SIZE_SHIFT 0
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#define TEGRA186_ASRC_STREAM_STATEBUF_CONFIG_SIZE_MASK (0xFFFF << TEGRA186_ASRC_STREAM_STATEBUF_CONFIG_SIZE_SHIFT)
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#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CONFIG_SIZE_SHIFT 0
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#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CONFIG_SIZE_MASK (0xFFFF << TEGRA186_ASRC_STREAM_INSAMPLEBUF_CONFIG_SIZE_SHIFT)
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#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CONFIG_SIZE_SHIFT 0
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#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CONFIG_SIZE_MASK (0xFFFF << TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CONFIG_SIZE_SHIFT)
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#define TEGRA186_ASRC_GLOBAL_CONFIG_FRAC_28BIT_PRECISION 0
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#define TEGRA186_ASRC_GLOBAL_CONFIG_FRAC_32BIT_PRECISION 1
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#define TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_MAX_CHANNELS_SHIFT 24
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#define TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_MAX_CHANNELS_MASK (0xFF << TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_MAX_CHANNELS_SHIFT)
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#define TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_BLOCK_SIZE_SHIFT 16
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#define TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_BLOCK_SIZE_MASK (0xFF << TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_BLOCK_SIZE_SHIFT)
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#define TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_SIZE_SHIFT 0
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#define TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_SIZE_MASK (0xFFFF << TEGRA186_ASRC_STREAM_GLOBAL_SCRATCH_CONFIG_SIZE_SHIFT)
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#define TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK 0x1F
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#define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK 0xFFFFFFFF
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#define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX 0x7FFFFFFF
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enum asrc_task_event {
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STREAM_DISABLE,
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STREAM_ENABLE,
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};
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struct tegra210_xbar_cif_conf;
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struct tegra186_asrc_lane {
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unsigned int int_part;
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unsigned int frac_part;
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int ratio_source;
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unsigned int hwcomp_disable;
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unsigned int input_thresh;
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unsigned int output_thresh;
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};
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struct tegra186_asrc {
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struct regmap *regmap;
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struct tegra186_asrc_lane lane[6];
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struct tasklet_struct tasklet;
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struct list_head task_desc;
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int active_dai_count;
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};
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int tegra186_asrc_set_source(int id, int source);
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int tegra186_asrc_event(int id, enum asrc_task_event event, int status);
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int tegra186_asrc_update_ratio(int id, int inte, int frac);
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void tegra186_asrc_handle_arad_unlock(int stream_id, int action);
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#endif
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