224 lines
10 KiB
C
224 lines
10 KiB
C
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/*
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* tegra210_i2s_alt.h - Definitions for Tegra210 I2S driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_I2S_ALT_H__
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#define __TEGRA210_I2S_ALT_H__
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/* Register offsets from TEGRA210_I2S*_BASE */
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#define TEGRA210_I2S_AXBAR_RX_ENABLE 0x0
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#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET 0x4
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#define TEGRA210_I2S_AXBAR_RX_STATUS 0x0c
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#define TEGRA210_I2S_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA210_I2S_AXBAR_RX_INT_MASK 0x14
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#define TEGRA210_I2S_AXBAR_RX_INT_SET 0x18
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#define TEGRA210_I2S_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA210_I2S_AXBAR_RX_CIF_CTRL 0x20
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#define TEGRA210_I2S_AXBAR_RX_CTRL 0x24
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#define TEGRA210_I2S_AXBAR_RX_SLOT_CTRL 0x28
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#define TEGRA210_I2S_AXBAR_RX_CLK_TRIM 0x2c
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#define TEGRA210_I2S_AXBAR_RX_CYA 0x30
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#define TEGRA210_I2S_AXBAR_RX_CIF_FIFO_STATUS 0x34
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#define TEGRA210_I2S_AXBAR_TX_ENABLE 0x40
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#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET 0x44
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#define TEGRA210_I2S_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_I2S_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_I2S_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_I2S_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_I2S_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_I2S_AXBAR_TX_CIF_CTRL 0x60
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#define TEGRA210_I2S_AXBAR_TX_CTRL 0x64
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#define TEGRA210_I2S_AXBAR_TX_SLOT_CTRL 0x68
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#define TEGRA210_I2S_AXBAR_TX_CLK_TRIM 0x6c
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#define TEGRA210_I2S_AXBAR_TX_CYA 0x70
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#define TEGRA210_I2S_AXBAR_TX_CIF_FIFO_STATUS 0x74
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#define TEGRA210_I2S_ENABLE 0x80
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#define TEGRA210_I2S_SOFT_RESET 0x84
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#define TEGRA210_I2S_CG 0x88
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#define TEGRA210_I2S_STATUS 0x8c
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#define TEGRA210_I2S_INT_STATUS 0x90
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#define TEGRA210_I2S_CTRL 0xa0
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#define TEGRA210_I2S_TIMING 0xa4
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#define TEGRA210_I2S_SLOT_CTRL 0xa8
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#define TEGRA210_I2S_CLK_TRIM 0xac
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#define TEGRA210_I2S_CYA 0xb0
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/*
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* I2S_AXBAAR_RX registers are with respect to AXBAR.
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* The data is coming from AXBAR to I2S for playback.
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*/
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/* Fields in TEGRA210_I2S_AXBAR_RX_ENABLE */
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#define TEGRA210_I2S_AXBAR_RX_EN_SHIFT 0
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#define TEGRA210_I2S_AXBAR_RX_EN (1 << TEGRA210_I2S_AXBAR_RX_EN_SHIFT)
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/* Fields in TEGRA210_I2S_AXBAR_RX_CTRL */
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#define TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_SHIFT 8
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#define TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_MASK (0x7ff << TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_MASK_BITS_SHIFT 4
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#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT 1
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#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_NOHIGHZ (0 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_HIGHZ (1 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_HIGHZ_ON_HALF_BIT_CLK (2 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT 0
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#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_MASK (1 << TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_MSB_FIRST (0 << TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_LSB_FIRST (1 << TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT)
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/*
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* I2S_AXBAAR_TX registers are with respect to AXBAR.
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* The data is goint to AXBAR from I2S for capture.
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*/
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/* Fields in TEGRA210_I2S_AXBAR_TX_ENABLE */
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#define TEGRA210_I2S_AXBAR_TX_EN_SHIFT 0
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#define TEGRA210_I2S_AXBAR_TX_EN (1 << TEGRA210_I2S_AXBAR_TX_EN_SHIFT)
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/* Fields in TEGRA210_I2S_AXBAR_TX_CTRL */
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#define TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_SHIFT 8
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#define TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_MASK (0x7ff << TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_MASK_BITS_SHIFT 4
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#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT 1
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#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_NOHIGHZ (0 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_HIGHZ (1 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_HIGHZ_ON_HALF_BIT_CLK (2 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT 0
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#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_MASK (1 << TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_MSB_FIRST (0 << TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_LSB_FIRST (1 << TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT)
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/* Fields in TEGRA210_I2S_ENABLE */
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#define TEGRA210_I2S_EN_SHIFT 0
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#define TEGRA210_I2S_EN_MASK (1 << TEGRA210_I2S_EN_SHIFT)
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#define TEGRA210_I2S_EN (1 << TEGRA210_I2S_EN_SHIFT)
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/* Fields in TEGRA210_I2S_CTRL */
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#define TEGRA210_I2S_CTRL_FSYNC_WIDTH_SHIFT 24
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#define TEGRA210_I2S_CTRL_FSYNC_WIDTH_MASK (0xff << TEGRA210_I2S_CTRL_FSYNC_WIDTH_SHIFT)
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#define TEGRA210_I2S_POS_EDGE 0
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#define TEGRA210_I2S_NEG_EDGE 1
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#define TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT 20
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#define TEGRA210_I2S_CTRL_EDGE_CTRL_MASK (1 << TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT)
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#define TEGRA210_I2S_CTRL_EDGE_CTRL_POS_EDGE (TEGRA210_I2S_POS_EDGE << TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT)
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#define TEGRA210_I2S_CTRL_EDGE_CTRL_NEG_EDGE (TEGRA210_I2S_NEG_EDGE << TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT)
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#define TEGRA210_I2S_CTRL_PIPE_MACRO_EN_SHIFT 19
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#define TEGRA210_I2S_CTRL_PIPE_MACRO_EN (1 << TEGRA210_I2S_CTRL_PIPE_MACRO_EN_SHIFT)
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#define TEGRA210_I2S_FRAME_FORMAT_LRCK 0
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#define TEGRA210_I2S_FRAME_FORMAT_FSYNC 1
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#define TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT 12
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#define TEGRA210_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define TEGRA210_I2S_CTRL_FRAME_FORMAT_LRCK_MODE (TEGRA210_I2S_FRAME_FORMAT_LRCK << TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define TEGRA210_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE (TEGRA210_I2S_FRAME_FORMAT_FSYNC << TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define TEGRA210_I2S_CTRL_MASTER_EN_SHIFT 10
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#define TEGRA210_I2S_CTRL_MASTER_EN_MASK (1 << TEGRA210_I2S_CTRL_MASTER_EN_SHIFT)
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#define TEGRA210_I2S_CTRL_MASTER_EN (1 << TEGRA210_I2S_CTRL_MASTER_EN_SHIFT)
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#define TEGRA210_I2S_CTRL_SLAVE_EN (1 << TEGRA210_I2S_CTRL_MASTER_EN_SHIFT)
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#define TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT 9
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#define TEGRA210_I2S_CTRL_LRCK_POLARITY_MASK (1 << TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT)
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#define TEGRA210_I2S_CTRL_LRCK_POLARITY_LOW (0 << TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT)
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#define TEGRA210_I2S_CTRL_LRCK_POLARITY_HIGH (1 << TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT)
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#define TEGRA210_I2S_CTRL_LPBK_SHIFT 8
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#define TEGRA210_I2S_CTRL_LPBK_MASK (1 << TEGRA210_I2S_CTRL_LPBK_SHIFT)
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#define TEGRA210_I2S_CTRL_LPBK_EN (1 << TEGRA210_I2S_CTRL_LPBK_SHIFT)
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#define TEGRA210_I2S_BITS_8 1
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#define TEGRA210_I2S_BITS_12 2
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#define TEGRA210_I2S_BITS_16 3
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#define TEGRA210_I2S_BITS_20 4
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#define TEGRA210_I2S_BITS_24 5
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#define TEGRA210_I2S_BITS_28 6
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#define TEGRA210_I2S_BITS_32 7
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#define TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT 0
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#define TEGRA210_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_8 (TEGRA210_I2S_BITS_8 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_12 (TEGRA210_I2S_BITS_12 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_16 (TEGRA210_I2S_BITS_16 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_20 (TEGRA210_I2S_BITS_20 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_24 (TEGRA210_I2S_BITS_24 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_28 (TEGRA210_I2S_BITS_28 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA210_I2S_CTRL_BIT_SIZE_32 (TEGRA210_I2S_BITS_32 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
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/* Fields in TEGRA210_I2S_TIMING */
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#define TEGRA210_I2S_TIMING_NON_SYM_EN_SHIFT 12
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#define TEGRA210_I2S_TIMING_NON_SYM_EN (1 << TEGRA210_I2S_TIMING_NON_SYM_EN_SHIFT)
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#define TEGRA210_I2S_TIMING_CHANNEL_BIT_CNT_MASK 0x3ff
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#define TEGRA210_I2S_TIMING_CHANNEL_BIT_CNT_SHIFT 0
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/* Fields in TEGRA210_I2S_RX_SOFT_RESET */
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#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT 0
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#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_MASK (1 << TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_EN (1 << TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT)
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#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_DEFAULT (0 << TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT)
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/* Fields in TEGRA210_I2S_TX_SOFT_RESET */
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#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT 0
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#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_MASK (1 << TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_EN (1 << TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT)
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#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_DEFAULT (0 << TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT)
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/* Fields in TEGRA210_I2S_SLOT_CTRL */
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#define TEGRA210_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 0
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#define TEGRA210_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK 0xf
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#define TEGRA210_I2S_RX_FIFO_DEPTH 64
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enum tegra210_i2s_path {
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I2S_RX_PATH,
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I2S_TX_PATH,
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I2S_PATHS,
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};
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struct tegra210_i2s {
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struct clk *clk_i2s;
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struct clk *clk_sync_input;
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struct regmap *regmap;
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const char *prod_name;
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struct regulator_bulk_data *supplies;
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int num_supplies;
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int bclk_ratio;
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int format_in;
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int codec_bit_format;
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int sample_rate_via_control;
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int channels_via_control;
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int stereo_to_mono[I2S_PATHS];
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int mono_to_stereo[I2S_PATHS];
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unsigned int fsync_width;
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unsigned int tx_mask;
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unsigned int rx_mask;
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bool loopback;
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unsigned int format;
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bool enable_cya;
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unsigned int rx_fifo_th; /* should be programmed interms of frames */
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};
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#endif
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