98 lines
3.1 KiB
C
98 lines
3.1 KiB
C
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/*
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* tegra210_sfc_alt.h - Definitions for Tegra210 SFC driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_SFC_ALT_H__
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#define __TEGRA210_SFC_ALT_H__
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/*
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* SFC_AXBAR_RX registers are with respect to AXBAR.
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* The data is coming from AXBAR to SFC for playback.
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*/
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#define TEGRA210_SFC_AXBAR_RX_STATUS 0x0c
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#define TEGRA210_SFC_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA210_SFC_AXBAR_RX_INT_MASK 0x14
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#define TEGRA210_SFC_AXBAR_RX_INT_SET 0x18
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#define TEGRA210_SFC_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA210_SFC_AXBAR_RX_CIF_CTRL 0x20
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#define TEGRA210_SFC_AXBAR_RX_FREQ 0x24
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#define TEGRA210_SFC_AXBAR_RX_CYA 0x28
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#define TEGRA210_SFC_AXBAR_RX_DBG 0x2c
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/*
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* SFC_AXBAR_TX registers are with respect to AXBAR.
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* The data is going out of SFC for playback.
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*/
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#define TEGRA210_SFC_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_SFC_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_SFC_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_SFC_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_SFC_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_SFC_AXBAR_TX_CIF_CTRL 0x60
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#define TEGRA210_SFC_AXBAR_TX_FREQ 0x64
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#define TEGRA210_SFC_AXBAR_TX_CYA 0x68
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#define TEGRA210_SFC_AXBAR_TX_DBG 0x6c
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/* Register offsets from TEGRA210_SFC*_BASE */
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#define TEGRA210_SFC_ENABLE 0x80
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#define TEGRA210_SFC_SOFT_RESET 0x84
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#define TEGRA210_SFC_CG 0x88
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#define TEGRA210_SFC_STATUS 0x8c
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#define TEGRA210_SFC_INT_STATUS 0x90
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#define TEGRA210_SFC_CYA 0x94
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#define TEGRA210_SFC_DBG 0xac
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#define TEGRA210_SFC_COEF_RAM 0xbc
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#define TEGRA210_SFC_AHUBRAMCTL_SFC_CTRL 0xc0
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#define TEGRA210_SFC_AHUBRAMCTL_SFC_DATA 0xc4
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/* Fields in TEGRA210_SFC_ENABLE */
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#define TEGRA210_SFC_EN_SHIFT 0
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#define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
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#define TEGRA210_SFC_BITS_8 1
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#define TEGRA210_SFC_BITS_12 2
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#define TEGRA210_SFC_BITS_16 3
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#define TEGRA210_SFC_BITS_20 4
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#define TEGRA210_SFC_BITS_24 5
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#define TEGRA210_SFC_BITS_28 6
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#define TEGRA210_SFC_BITS_32 7
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#define TEGRA210_SFC_NUM_RATES 13
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/* Fields in TEGRA210_SFC_COEF_RAM */
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#define TEGRA210_SFC_COEF_RAM_COEF_RAM_EN BIT(0)
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#define TEGRA210_SFC_SOFT_RESET_EN BIT(0)
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/* SRC coefficients */
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#define TEGRA210_SFC_COEF_RAM_DEPTH 64
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struct tegra210_sfc {
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int srate_in;
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int srate_out;
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int format_in;
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int format_out;
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struct regmap *regmap;
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struct snd_pcm_hw_params in_hw_params;
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struct snd_pcm_hw_params out_hw_params;
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int stereo_conv_input;
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int mono_conv_output;
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unsigned int channels_via_control;
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};
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#endif
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