81 lines
2.0 KiB
Plaintext
81 lines
2.0 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device-tree overlay for MCP251x CAN Controller
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*
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* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-common/jetson/tegra210-p3448-0000-p3449-0000-a02.h>
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#include <overlays/jetson-mcp251x.dts>
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/ {
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fragment@2 {
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target = <&pinmux>;
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__overlay__ {
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hdr40_pinmux: header-40pin-pinmux {
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pin37 {
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nvidia,pins = HDR40_PIN37;
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pin22 {
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nvidia,pins = HDR40_PIN22;
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pin13 {
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nvidia,pins = HDR40_PIN13;
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pin18 {
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nvidia,pins = HDR40_PIN18;
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pin16 {
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nvidia,pins = HDR40_PIN16;
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nvidia,function = "spi2";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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};
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};
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};
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fragment@3 {
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target = <&hdr40_spi2>;
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__overlay__ {
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spi@0 {
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compatible = "microchip,mcp2515";
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reg = <0x0>;
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spi-max-frequency = <10000000>;
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x7>;
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clocks = <&can_clock>;
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interrupt-parent = <&gpio>;
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interrupts = <HDR40_PIN32_GPIO 0x1>;
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controller-data {
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nvidia,cs-setup-clk-count = <0x1e>;
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nvidia,cs-hold-clk-count = <0x1e>;
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nvidia,rx-clk-tap-delay = <0x1f>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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};
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};
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