115 lines
2.5 KiB
Plaintext
115 lines
2.5 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Jetson Device-tree overlay for FE-PI Audio V1 and Z V2.
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*
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* Copyright (c) 2019-2021 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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/ {
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overlay-name = "FE-PI Audio V1 and Z V2";
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jetson-header-name = "Jetson 40pin Header";
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compatible = JETSON_COMPATIBLE;
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fragment@0 {
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target-path = "/";
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__overlay__ {
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clocks {
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sgtl5000_mclk: sgtl5000_mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12288000>;
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clock-output-names = "sgtl5000-mclk";
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status = "okay";
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};
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};
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};
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};
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fragment@1 {
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target = <&hdr40_i2c1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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sgtl5000: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&sgtl5000_mclk>;
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micbias-resistor-k-ohms = <2>;
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micbias-voltage-m-volts = <3000>;
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VDDA-supply = <&hdr40_vdd_3v3>;
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VDDIO-supply = <&hdr40_vdd_3v3>;
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status = "okay";
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};
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};
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};
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fragment@2 {
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target = <&tegra_sound>;
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__overlay__ {
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nvidia,audio-routing =
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"x Headphone", "x HP_OUT",
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"x MIC_IN", "x Mic",
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"x ADC", "x Mic Bias",
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"x LINE_IN", "x Line In",
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"x Line Out", "x LINE_OUT";
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};
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};
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fragment@3 {
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target = <&hdr40_snd_link_i2s>;
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__overlay__ {
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link-name = "fe-pi-audio-z-v2";
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codec-dai = <&sgtl5000>;
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codec-dai-name = "sgtl5000";
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bitclock-master;
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frame-master;
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};
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};
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fragment@4 {
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target = <&pinmux>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&jetson_io_pinmux>;
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jetson_io_pinmux: exp-header-pinmux {
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hdr40-pin12 {
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nvidia,pins = HDR40_PIN12;
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nvidia,function = HDR40_I2S;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin35 {
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nvidia,pins = HDR40_PIN35;
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nvidia,function = HDR40_I2S;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin38 {
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nvidia,pins = HDR40_PIN38;
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nvidia,function = HDR40_I2S;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin40 {
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nvidia,pins = HDR40_PIN40;
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nvidia,function = HDR40_I2S;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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};
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};
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};
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};
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