135 lines
6.3 KiB
Plaintext
135 lines
6.3 KiB
Plaintext
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/*
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* arch/arm/boot/dts/panel-b-1440-1600-3-5.dtsi
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*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <dt-bindings/display/tegra-dc.h>
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#include <dt-bindings/display/tegra-panel.h>
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/ {
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i2c@31c0000 {
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tc358870@0f {
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panel-b-1440-1600-3-5 {
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status = "okay";
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compatible = "b,1440-1600-3-5";
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nvidia,panel-id = <0>;
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nvidia,dsi-n-data-lanes = <8>;
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nvidia,dsi-init-cmd =
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/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
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/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
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/* For DSI packets each DT cell is interpreted as u8 not u32 */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFF 0xE0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0X53 0x22 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0XFF 0x25 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC4 0x10 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x60 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x40 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0x3C 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFF 0x10 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC0 0x80 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x08 0x0 0x0 0x05 0x00 0xBE 0x01 0xC6 0x00 0x32 0x00 0x0 0x0>,
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/* Set display mode to Video mode */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xBB 0x03 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x00 0x0>,
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/* Scan direction */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x00 0x0>;
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nvidia,dsi-n-init-cmd = <16>;
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nvidia,dsi-postvideo-cmd =
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/* MCAP */
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<TEGRA_DSI_PACKET_CMD DSI_GENERIC_SHORT_WRITE_2_PARAMS 0xB0 0x00 0x0>,
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<TEGRA_DSI_DELAY_US 200>,
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/* Interface Setting */
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<TEGRA_DSI_PACKET_CMD DSI_GENERIC_SHORT_WRITE_2_PARAMS 0xB3 0x14 0x0>,
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<TEGRA_DSI_DELAY_US 200>,
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/* MCAP */
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<TEGRA_DSI_PACKET_CMD DSI_GENERIC_SHORT_WRITE_2_PARAMS 0xB0 0x03 0x0>,
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<TEGRA_DSI_DELAY_US 200>,
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<TEGRA_DSI_DELAY_US 200>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 200>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
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<TEGRA_DSI_DELAY_US 200>;
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nvidia,dsi-n-postvideo-cmd = <11>;
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nvidia,dsi-suspend-cmd =
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 20>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 20>;
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nvidia,dsi-n-suspend-cmd = <4>;
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};
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};
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};
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i2c@31e0000 {
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tc358870@0f {
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panel-b-1440-1600-3-5 {
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status = "okay";
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compatible = "b,1440-1600-3-5";
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nvidia,panel-id = <1>;
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nvidia,dsi-n-data-lanes = <8>;
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nvidia,dsi-init-cmd =
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/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
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/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
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/* For DSI packets each DT cell is interpreted as u8 not u32 */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFF 0xE0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0X53 0x22 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0XFF 0x25 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC4 0x10 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x62 0x60 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x66 0x40 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x67 0x3C 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFF 0x10 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xFB 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC0 0x80 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x08 0x0 0x0 0x05 0x00 0xBE 0x01 0xC6 0x00 0x32 0x00 0x0 0x0>,
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/* Set display mode to Video mode */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xBB 0x03 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x00 0x0>,
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/* Reverse scan direction for 2nd panel */
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x03 0x0>;
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nvidia,dsi-n-init-cmd = <16>;
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nvidia,dsi-postvideo-cmd =
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/* MCAP */
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<TEGRA_DSI_PACKET_CMD DSI_GENERIC_SHORT_WRITE_2_PARAMS 0xB0 0x00 0x0>,
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<TEGRA_DSI_DELAY_US 200>,
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/* Interface Setting */
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<TEGRA_DSI_PACKET_CMD DSI_GENERIC_SHORT_WRITE_2_PARAMS 0xB3 0x14 0x0>,
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<TEGRA_DSI_DELAY_US 200>,
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/* MCAP */
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<TEGRA_DSI_PACKET_CMD DSI_GENERIC_SHORT_WRITE_2_PARAMS 0xB0 0x03 0x0>,
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<TEGRA_DSI_DELAY_US 200>,
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<TEGRA_DSI_DELAY_US 200>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 200>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
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<TEGRA_DSI_DELAY_US 200>;
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nvidia,dsi-n-postvideo-cmd = <11>;
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nvidia,dsi-suspend-cmd =
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 20>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 20>;
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nvidia,dsi-n-suspend-cmd = <4>;
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};
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};
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};
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};
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