148 lines
7.6 KiB
Plaintext
148 lines
7.6 KiB
Plaintext
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/*
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* arch/arm/boot/dts/panel-o-720p-6-0.dtsi
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <dt-bindings/display/tegra-dc.h>
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#include <dt-bindings/display/tegra-panel.h>
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/ {
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host1x {
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dsi {
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panel_o_720p_6_0: panel-o-720p-6-0 {
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status = "disabled";
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compatible = "o,720-1280-6-0";
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nvidia,dsi-instance = <DSI_INSTANCE_0>;
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nvidia,dsi-n-data-lanes = <4>;
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nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
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nvidia,dsi-refresh-rate = <60>;
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nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
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nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>;
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nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
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nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
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nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
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nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
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nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
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nvidia,dsi-init-cmd = <TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x4 0x0 0x0 0xb9 0xff 0x83 0x94 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x10 0x0 0x0 0xb1 0x41 0x0c 0x4c 0x33 0xa4 0x79 0xf1 0x81 0x32 0xde 0x23
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0x80 0xc0 0xd2 0x41 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xd 0x0 0x0 0xb2 0x0 0x64 0x14 0x09 0x22 0x1b 0x08 0x08 0x1c 0x4d 0x31
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0x0 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x17 0x0 0x0 0xb4 0x0 0xff 0x52 0x3e 0x52 0x3e 0x0 0x0 0x0 0x7f 0x0
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0x6e 0x52 0x3e 0x52 0x3e 0x0 0x0 0x0 0x7f 0x0 0x6e 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x7 0x0 0x0 0xbb 0x0 0x0 0x0 0x0 0x0 0x80 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x4 0x0 0x0 0xc6 0x7e 0x58 0x20 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x5 0x0 0x0 0xc7 0x0 0x0 0x20 0x80 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xcc 0x05 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x35 0x0 0x0 0xd3 0x0 0x0f 0x0 0x04 0x7f 0x20 0x0 0x32 0x15 0x18 0x0
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0x0e 0x10 0x10 0x0e 0x05 0x18 0x0 0x0 0x0 0x0 0x0 0x27 0x22 0x10 0x10
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0x27 0x0 0x0 0x0 0x15 0x0 0x06 0x0 0x0a 0x0 0x01 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x03 0x05 0x0f 0x0 0x0 0x07 0x0 0x0 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x2d 0x0 0x0 0xd5 0x18 0x18 0x26 0x27 0x20 0x21 0x0 0x01 0x02 0x03 0x04
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0x05 0x06 0x07 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18
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0x18 0x18 0x18 0x18 0x18 0x18 0x1d 0x1d 0x18 0x18 0x18 0x18 0x1c 0x1c 0x18
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0x18 0x18 0x18 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x2d 0x0 0x0 0xd6 0x18 0x18 0x26 0x27 0x21 0x20 0x07 0x06 0x05 0x04 0x03
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0x02 0x01 0x0 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18
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0x18 0x18 0x18 0x18 0x18 0x18 0x1d 0x1d 0x18 0x18 0x18 0x18 0x1c 0x1c 0x18
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0x18 0x18 0x18 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x19 0x0 0x0 0xd8 0xaa 0xaa 0xaa 0xaa 0xeb 0xaa 0xaa 0xaa 0xaa 0xaa 0xeb
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0xaa 0xaa 0xaa 0xaa 0xaa 0xeb 0xaa 0xaa 0xaa 0xaa 0xaa 0xeb 0xaa 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x01 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x27 0x0 0x0 0xd8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x02 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x0f 0x0 0x0 0xd8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x2b 0x0 0x0 0xe0 0x00 0x08 0x0e 0x2c 0x2f 0x3d 0x1a 0x35 0x07 0x0b 0x0d
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0x18 0x0e 0x11 0x13 0x11 0x13 0x06 0x12 0x12 0x16 0x00 0x08 0x0e 0x2c 0x2f
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0x3d 0x1a 0x35 0x07 0x0b 0x0d 0x18 0x0e 0x11 0x13 0x11 0x13 0x06 0x12 0x12
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0x16 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x0 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x2c 0x0 0x0 0xc1 0x01 0x00 0x08 0x0e 0x16 0x1d 0x23 0x28 0x30 0x37 0x40
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0x47 0x4e 0x55 0x5c 0x63 0x6a 0x72 0x7a 0x81 0x88 0x8f 0x96 0x9d 0xa4 0xab
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0xb2 0xb9 0xc1 0xc8 0xcf 0xd8 0xde 0xe5 0x04 0x7d 0xfc 0x03 0x80 0x6e 0xe8
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0xf3 0x00 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x1 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x2b 0x0 0x0 0xc1 0x00 0x08 0x10 0x18 0x20 0x27 0x2f 0x37 0x3f 0x47 0x4f
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0x57 0x5f 0x67 0x6f 0x77 0x7f 0x87 0x8f 0x97 0x9f 0xa7 0xaf 0xb7 0xbf 0xc7
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0xd0 0xd8 0xe0 0xe8 0xef 0xf7 0xff 0x01 0x79 0x15 0x55 0x90 0x56 0xf0 0x0f
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0xc0 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x2 0x0>,
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<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0x2b 0x0 0x0 0xc1 0x00 0x08 0x0f 0x17 0x1f 0x26 0x2d 0x35 0x3d 0x46 0x4d
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0x55 0x5d 0x65 0x6c 0x74 0x7c 0x84 0x8b 0x93 0x9b 0xa2 0xa9 0xb2 0xba 0xc2
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0xcb 0xd2 0xda 0xe2 0xe9 0xf1 0xf9 0x0a 0x4a 0x9e 0x8e 0x9e 0xae 0xe3 0x8b
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0x40 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_1_PARAM 0xbd 0x0 0x0>,
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<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 200>, //180ms + 20ms
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/* TODO, Do we need to find a way to set set_display_on after "operate DSI_A in video mode"? */
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<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>;
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nvidia,dsi-n-init-cmd = <29>;
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nvidia,dsi-suspend-cmd = <0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 50>,
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<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
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<TEGRA_DSI_DELAY_MS 10>;
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nvidia,dsi-n-suspend-cmd = <4>;
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disp-default-out {
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nvidia,out-type = <TEGRA_DC_OUT_DSI>;
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/* TODO check real physical width and height in mm unit */
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nvidia,out-width = <80>;
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nvidia,out-height = <142>;
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nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
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nvidia,out-xres = <720>;
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nvidia,out-yres = <1280>;
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};
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display-timings {
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720x1280-24 {
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clock-frequency = <76693500>; /* (720+121+134) x (1280+9+22) x 60 */
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hactive = <720>;
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vactive = <1280>;
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hfront-porch = <121>; /* 90.75 Byte clk / 0.75 = 121 */
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/* TODO, doc mentioned HS+HBP to 100 Byte clk (133.33...)
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* Once hsync_width and HBP are clear, need to set these again */
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hback-porch = <67>;
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hsync-len = <67>;
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vfront-porch = <9>;
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/* TODO, doc mentioned VBP only to 22.
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* Once vsync_width is clear, need to set VBP and vsync_width again */
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vback-porch = <21>;
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vsync-len = <1>;
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nvidia,h-ref-to-sync = <1>;
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nvidia,v-ref-to-sync = <1>;
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};
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};
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smartdimmer {
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status = "disabled";
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};
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};
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};
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};
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backlight {
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panel_o_720p_6_0_bl: panel-o-720p-6-0-bl {
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status = "disabled";
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compatible = "o,720-1280-6-0-bl";
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pwms = <&tegra_pwm 1 50000>;
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max-brightness = <255>;
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default-brightness = <224>;
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};
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};
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};
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